[llvm-commits] [llvm] r159548 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Andrew Trick]

Author: atrick
Date: Mon Jul  2 14:12:29 2012
New Revision: 159548

URL: http://llvm.org/viewvc/llvm-project?rev=159548&view=rev
Log:
Revert accidental checkin.

My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=159548&r1=159547&r2=159548&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Jul  2 14:12:29 2012
@@ -3057,10 +3057,9 @@
   unsigned Class = MCID.getSchedClass();
 
   // For instructions with variable uops, use uops as latency.
-  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) {
-    dbgs() << "UOPS " << getNumMicroOps(ItinData, MI) << " " << *MI << '\n';
+  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
     return getNumMicroOps(ItinData, MI);
-  }
+
   // For the common case, fall back on the itinerary's latency.
   unsigned Latency = ItinData->getStageLatency(Class);