[llvm-commits] [llvm] r159407 - in /llvm/trunk: include/llvm/MC/MCInstrItineraries.h lib/CodeGen/MachineScheduler.cpp

[Andrew Trick]

Author: atrick
Date: Thu Jun 28 22:23:22 2012
New Revision: 159407

URL: http://llvm.org/viewvc/llvm-project?rev=159407&view=rev
Log:
misched: count micro-ops toward the issue limit.

Modified:
    llvm/trunk/include/llvm/MC/MCInstrItineraries.h
    llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Modified: llvm/trunk/include/llvm/MC/MCInstrItineraries.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrItineraries.h?rev=159407&r1=159406&r2=159407&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrItineraries.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrItineraries.h Thu Jun 28 22:23:22 2012
@@ -313,13 +313,13 @@
     return UseCycle;
   }
 
-  /// isMicroCoded - Return true if the instructions in the given class decode
-  /// to more than one micro-ops.
-  bool isMicroCoded(unsigned ItinClassIndx) const {
+  /// getNumMicroOps - Return the number of micro-ops that the given class
+  /// decodes to. Return -1 for classes that require dynamic lookup via
+  /// TargetInstrInfo.
+  int getNumMicroOps(unsigned ItinClassIndx) const {
     if (isEmpty())
-      return false;
-    int UOps = Itineraries[ItinClassIndx].NumMicroOps;
-    return UOps < 0 || UOps > 1;
+      return 1;
+    return Itineraries[ItinClassIndx].NumMicroOps;
   }
 };
 

Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=159407&r1=159406&r2=159407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Thu Jun 28 22:23:22 2012
@@ -402,11 +402,16 @@
   }
 
   /// getIssueWidth - Return the max instructions per scheduling group.
-  ///
   unsigned getIssueWidth() const {
     return InstrItins ? InstrItins->Props.IssueWidth : 1;
   }
 
+  /// getNumMicroOps - Return the number of issue slots required for this MI.
+  unsigned getNumMicroOps(MachineInstr *MI) const {
+    int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
+    return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
+  }
+
 protected:
   void initRegPressure();
   void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
@@ -788,6 +793,8 @@
   /// current cycle in whichever direction at has moved, and maintains the state
   /// of "hazards" and other interlocks at the current cycle.
   struct SchedBoundary {
+    ScheduleDAGMI *DAG;
+
     ReadyQueue Available;
     ReadyQueue Pending;
     bool CheckPending;
@@ -806,7 +813,7 @@
     /// Pending queues extend the ready queues with the same ID and the
     /// PendingFlag set.
     SchedBoundary(unsigned ID, const Twine &Name):
-      Available(ID, Name+".A"),
+      DAG(0), Available(ID, Name+".A"),
       Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
       CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
       MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
@@ -821,7 +828,7 @@
 
     void bumpCycle();
 
-    void bumpNode(SUnit *SU, unsigned IssueWidth);
+    void bumpNode(SUnit *SU);
 
     void releasePending();
 
@@ -874,6 +881,8 @@
 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
   DAG = dag;
   TRI = DAG->TRI;
+  Top.DAG = dag;
+  Bot.DAG = dag;
 
   // Initialize the HazardRecognizers.
   const TargetMachine &TM = DAG->MF.getTarget();
@@ -940,7 +949,8 @@
 
 /// Move the boundary of scheduled code by one cycle.
 void ConvergingScheduler::SchedBoundary::bumpCycle() {
-  IssueCount = 0;
+  unsigned Width = DAG->getIssueWidth();
+  IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
 
   assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
   unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
@@ -965,8 +975,7 @@
 }
 
 /// Move the boundary of scheduled code by one SUnit.
-void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU,
-                                                  unsigned IssueWidth) {
+void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
   // Update the reservation table.
   if (HazardRec->isEnabled()) {
     if (!isTop() && SU->isCall) {
@@ -977,8 +986,8 @@
     HazardRec->EmitInstruction(SU);
   }
   // Check the instruction group size limit.
-  ++IssueCount;
-  if (IssueCount == IssueWidth) {
+  IssueCount += DAG->getNumMicroOps(SU->getInstr());
+  if (IssueCount >= DAG->getIssueWidth()) {
     DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
     bumpCycle();
   }
@@ -1277,11 +1286,11 @@
 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
   if (IsTopNode) {
     SU->TopReadyCycle = Top.CurrCycle;
-    Top.bumpNode(SU, DAG->getIssueWidth());
+    Top.bumpNode(SU);
   }
   else {
     SU->BotReadyCycle = Bot.CurrCycle;
-    Bot.bumpNode(SU, DAG->getIssueWidth());
+    Bot.bumpNode(SU);
   }
 }