[llvm-commits] [llvm] r159166 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/sub-cmp-peephole.ll

[Manman Ren]

Author: mren
Date: Mon Jun 25 16:49:38 2012
New Revision: 159166

URL: http://llvm.org/viewvc/llvm-project?rev=159166&view=rev
Log:
ARM: update peephole optimization.

More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to 
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".

rdar: 11725965

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=159166&r1=159165&r2=159166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Jun 25 16:49:38 2012
@@ -1875,7 +1875,9 @@
     }
 
     // Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1).
-    if (SrcReg2 != 0 && Instr.getOpcode() == ARM::SUBrr &&
+    if (SrcReg2 != 0 &&
+        (Instr.getOpcode() == ARM::SUBrr ||
+         Instr.getOpcode() == ARM::t2SUBrr) &&
         ((Instr.getOperand(1).getReg() == SrcReg &&
           Instr.getOperand(2).getReg() == SrcReg2) ||
          (Instr.getOperand(1).getReg() == SrcReg2 &&
@@ -1976,6 +1978,12 @@
           case ARMCC::LT:
           case ARMCC::GT:
           case ARMCC::LE:
+          case ARMCC::HS:
+          case ARMCC::LS:
+          case ARMCC::HI:
+          case ARMCC::LO:
+          case ARMCC::EQ:
+          case ARMCC::NE:
             // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
             // on CMP needs to be updated to be based on SUB.
             // Push the condition code operands to OperandsToUpdate.
@@ -2023,7 +2031,15 @@
       case ARMCC::GE: NewCC = ARMCC::LE; break;
       case ARMCC::LT: NewCC = ARMCC::GT; break;
       case ARMCC::GT: NewCC = ARMCC::LT; break;
-      case ARMCC::LE: NewCC = ARMCC::GT; break;
+      case ARMCC::LE: NewCC = ARMCC::GE; break;
+      case ARMCC::HS: NewCC = ARMCC::LS; break;
+      case ARMCC::LS: NewCC = ARMCC::HS; break;
+      case ARMCC::HI: NewCC = ARMCC::LO; break;
+      case ARMCC::LO: NewCC = ARMCC::HI; break;
+      case ARMCC::EQ:
+      case ARMCC::NE:
+        NewCC = CC;
+        break;
       }
       OperandsToUpdate[i]->setImm(NewCC);
     }

Modified: llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll?rev=159166&r1=159165&r2=159166&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll Mon Jun 25 16:49:38 2012
@@ -32,3 +32,15 @@
   %sub. = select i1 %cmp, i32 %sub, i32 %b
   ret i32 %sub.
 }
+
+; rdar://11725965
+define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: i:
+; CHECK: subs
+; CHECK-NOT: cmp
+  %cmp = icmp ult i32 %a, %b
+  %sub = sub i32 %b, %a
+  %sub. = select i1 %cmp, i32 %sub, i32 0
+  ret i32 %sub.
+}