[llvm-commits] [llvm] r158441 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/CodeGen/ARM/iabs.ll test/Transforms/InstCombine/and-fcmp.ll

[Manman Ren]

Author: mren
Date: Thu Jun 14 00:57:42 2012
New Revision: 158441

URL: http://llvm.org/viewvc/llvm-project?rev=158441&view=rev
Log:
InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).

uno && ueq was converted to ueq, it should be converted to uno.

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    llvm/trunk/test/CodeGen/ARM/iabs.ll
    llvm/trunk/test/Transforms/InstCombine/and-fcmp.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=158441&r1=158440&r2=158441&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jun 14 00:57:42 2012
@@ -995,9 +995,11 @@
       std::swap(Op0Ordered, Op1Ordered);
     }
     if (Op0Pred == 0) {
-      // uno && ueq -> uno && (uno || eq) -> ueq
+      // uno && ueq -> uno && (uno || eq) -> uno
       // ord && olt -> ord && (ord && lt) -> olt
-      if (Op0Ordered == Op1Ordered)
+      if (!Op0Ordered && (Op0Ordered == Op1Ordered))
+        return LHS;
+      if (Op0Ordered && (Op0Ordered == Op1Ordered))
         return RHS;
       
       // uno && oeq -> uno && (ord && eq) -> false

Modified: llvm/trunk/test/CodeGen/ARM/iabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/iabs.ll?rev=158441&r1=158440&r2=158441&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/iabs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/iabs.ll Thu Jun 14 00:57:42 2012
@@ -10,7 +10,25 @@
         %b = icmp sgt i32 %a, -1
         %abs = select i1 %b, i32 %a, i32 %tmp1neg
         ret i32 %abs
-; CHECK:  movs r0, r0
+; CHECK:  cmp
 ; CHECK:  rsbmi r0, r0, #0
 ; CHECK:  bx lr
 }
+
+; rdar://11633193
+; 3 instructions will be generated for the following case:
+;   subs
+;   rsbmi
+;   bx
+define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: test2
+; CHECK-NEXT: subs
+; CHECK-NEXT: rsbmi
+; CHECK-NEXT: bx
+  %sub = sub nsw i32 %a, %b
+  %cmp = icmp sgt i32 %sub, -1
+  %sub1 = sub nsw i32 0, %sub
+  %cond = select i1 %cmp, i32 %sub, i32 %sub1
+  ret i32 %cond
+}

Modified: llvm/trunk/test/Transforms/InstCombine/and-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/and-fcmp.ll?rev=158441&r1=158440&r2=158441&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/and-fcmp.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/and-fcmp.ll Thu Jun 14 00:57:42 2012
@@ -66,3 +66,14 @@
 ; CHECK: t6
 ; CHECK: ret i8 0
 }
+
+define zeroext i8 @t7(float %x, float %y) nounwind {
+       %a = fcmp uno float %x, %y
+       %b = fcmp ult float %x, %y
+       %c = and i1 %a, %b
+       %retval = zext i1 %c to i8
+       ret i8 %retval
+; CHECK: t7
+; CHECK: fcmp uno
+; CHECK-NOT: fcmp ult
+}