[llvm-commits] [llvm] r158435 - in /llvm/trunk/test/CodeGen/Mips: 2010-07-20-Switch.ll i64arg.ll largeimmprinting.ll o32_cc_byval.ll o32_cc_vararg.ll
Akira Hatanaka
ahatanaka at mips.com
Wed Jun 13 18:21:01 PDT 2012
Author: ahatanak
Date: Wed Jun 13 20:21:00 2012
New Revision: 158435
URL: http://llvm.org/viewvc/llvm-project?rev=158435&view=rev
Log:
Fix test cases.
Modified:
llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
llvm/trunk/test/CodeGen/Mips/i64arg.ll
llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=158435&r1=158434&r2=158435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Wed Jun 13 20:21:00 2012
@@ -33,7 +33,6 @@
bb1: ; preds = %entry
ret i32 2
-; CHECK: STATIC-O32: $BB0_2
bb2: ; preds = %entry
ret i32 0
Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=158435&r1=158434&r2=158435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Wed Jun 13 20:21:00 2012
@@ -10,8 +10,8 @@
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK: lw $[[R2:[0-9]+]], 88($sp)
+; CHECK: lw $[[R3:[0-9]+]], 92($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=158435&r1=158434&r2=158435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Wed Jun 13 20:21:00 2012
@@ -7,7 +7,7 @@
define void @f() nounwind {
entry:
; CHECK: lui $at, 65534
-; CHECK: addiu $at, $at, -16
+; CHECK: addiu $at, $at, -24
; CHECK: addu $sp, $sp, $at
%agg.tmp = alloca %struct.S1, align 1
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=158435&r1=158434&r2=158435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Wed Jun 13 20:21:00 2012
@@ -13,16 +13,16 @@
; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)
; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
-; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
-; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
-; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: sw $[[R6]], 36($sp)
+; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: sw $[[R5]], 32($sp)
+; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: sw $[[R4]], 28($sp)
+; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: sw $[[R3]], 24($sp)
+; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: sw $[[R7]], 20($sp)
+; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: sw $[[R2]], 16($sp)
; CHECK: lw $7, 4($[[R0]])
; CHECK: lw $6, %lo(f1.s1)($[[R1]])
@@ -43,16 +43,16 @@
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: sw $6, 56($sp)
-; CHECK: lw $4, 80($sp)
-; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp)
-; CHECK: lw $[[R3:[0-9]+]], 64($sp)
-; CHECK: lw $[[R4:[0-9]+]], 68($sp)
-; CHECK: lw $[[R2:[0-9]+]], 60($sp)
-; CHECK: lh $[[R1:[0-9]+]], 58($sp)
-; CHECK: lb $[[R0:[0-9]+]], 56($sp)
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $7, 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: lw $4, 88($sp)
+; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 72($sp)
+; CHECK: lw $[[R4:[0-9]+]], 76($sp)
+; CHECK: lw $[[R2:[0-9]+]], 68($sp)
+; CHECK: lh $[[R1:[0-9]+]], 66($sp)
+; CHECK: lb $[[R0:[0-9]+]], 64($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R2]], 24($sp)
@@ -80,13 +80,13 @@
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: sw $6, 56($sp)
-; CHECK: sw $5, 52($sp)
-; CHECK: sw $4, 48($sp)
-; CHECK: lw $4, 48($sp)
-; CHECK: lw $[[R0:[0-9]+]], 60($sp)
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $7, 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $5, 60($sp)
+; CHECK: sw $4, 56($sp)
+; CHECK: lw $4, 56($sp)
+; CHECK: lw $[[R0:[0-9]+]], 68($sp)
; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@@ -99,13 +99,13 @@
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: sw $6, 56($sp)
-; CHECK: sw $5, 52($sp)
-; CHECK: lw $4, 60($sp)
-; CHECK: lw $[[R1:[0-9]+]], 80($sp)
-; CHECK: lb $[[R0:[0-9]+]], 52($sp)
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $7, 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $5, 60($sp)
+; CHECK: lw $4, 68($sp)
+; CHECK: lw $[[R1:[0-9]+]], 88($sp)
+; CHECK: lb $[[R0:[0-9]+]], 60($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 24($sp)
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=158435&r1=158434&r2=158435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Wed Jun 13 20:21:00 2012
@@ -29,11 +29,11 @@
ret i32 %tmp
; CHECK: va1:
-; CHECK: addiu $sp, $sp, -16
-; CHECK: sw $7, 28($sp)
-; CHECK: sw $6, 24($sp)
-; CHECK: sw $5, 20($sp)
-; CHECK: lw $2, 20($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: sw $5, 28($sp)
+; CHECK: lw $2, 28($sp)
}
; check whether the variable double argument will be accessed from the 8-byte
@@ -55,11 +55,11 @@
ret double %tmp
; CHECK: va2:
-; CHECK: addiu $sp, $sp, -16
-; CHECK: sw $7, 28($sp)
-; CHECK: sw $6, 24($sp)
-; CHECK: sw $5, 20($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: sw $5, 28($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 28
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -83,10 +83,10 @@
ret i32 %tmp
; CHECK: va3:
-; CHECK: addiu $sp, $sp, -16
-; CHECK: sw $7, 28($sp)
-; CHECK: sw $6, 24($sp)
-; CHECK: lw $2, 24($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: lw $2, 32($sp)
}
; double
@@ -106,11 +106,11 @@
ret double %tmp
; CHECK: va4:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: sw $6, 32($sp)
-; CHECK: addiu ${{[0-9]+}}, $sp, 32
-; CHECK: ldc1 $f0, 32($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: sw $7, 44($sp)
+; CHECK: sw $6, 40($sp)
+; CHECK: addiu ${{[0-9]+}}, $sp, 40
+; CHECK: ldc1 $f0, 40($sp)
}
; int
@@ -134,9 +134,9 @@
ret i32 %tmp
; CHECK: va5:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: lw $2, 36($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: sw $7, 44($sp)
+; CHECK: lw $2, 44($sp)
}
; double
@@ -160,9 +160,9 @@
ret double %tmp
; CHECK: va6:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
+; CHECK: addiu $sp, $sp, -32
+; CHECK: sw $7, 44($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -188,8 +188,8 @@
ret i32 %tmp
; CHECK: va7:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: lw $2, 40($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: lw $2, 48($sp)
}
; double
@@ -211,9 +211,9 @@
ret double %tmp
; CHECK: va8:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: addiu ${{[0-9]+}}, $sp, 48
-; CHECK: ldc1 $f0, 48($sp)
+; CHECK: addiu $sp, $sp, -40
+; CHECK: addiu ${{[0-9]+}}, $sp, 56
+; CHECK: ldc1 $f0, 56($sp)
}
; int
@@ -237,8 +237,8 @@
ret i32 %tmp
; CHECK: va9:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: lw $2, 52($sp)
+; CHECK: addiu $sp, $sp, -40
+; CHECK: lw $2, 60($sp)
}
; double
@@ -262,8 +262,8 @@
ret double %tmp
; CHECK: va10:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
+; CHECK: addiu $sp, $sp, -40
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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