[llvm-commits] [llvm] r158378 - /llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td
Akira Hatanaka
ahatanaka at mips.com
Tue Jun 12 19:37:54 PDT 2012
Author: ahatanak
Date: Tue Jun 12 21:37:54 2012
New Revision: 158378
URL: http://llvm.org/viewvc/llvm-project?rev=158378&view=rev
Log:
1. fix places where immed is used in place of imm to be consistent with
non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions
Patch by Reed Kotler.
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td?rev=158378&r1=158377&r2=158378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrFormats.td Tue Jun 12 21:37:54 2012
@@ -135,7 +135,7 @@
//===----------------------------------------------------------------------===//
-// Format I instruction class in Mips : <|opcode|immediate|>
+// Format I instruction class in Mips : <|opcode|imm11|>
//===----------------------------------------------------------------------===//
class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
@@ -150,7 +150,7 @@
}
//===----------------------------------------------------------------------===//
-// Format RI instruction class in Mips : <|opcode|rx|immed|>
+// Format RI instruction class in Mips : <|opcode|rx|imm8|>
//===----------------------------------------------------------------------===//
class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
@@ -209,7 +209,7 @@
}
//===----------------------------------------------------------------------===//
-// Format RRI instruction class in Mips : <|opcode|rx|ry|immed|>
+// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
//===----------------------------------------------------------------------===//
class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
@@ -251,7 +251,7 @@
}
//===----------------------------------------------------------------------===//
-// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|immed|>
+// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
//===----------------------------------------------------------------------===//
class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
@@ -295,7 +295,7 @@
}
//===----------------------------------------------------------------------===//
-// Format i8 instruction class in Mips : <|opcode|funct|immed>
+// Format i8 instruction class in Mips : <|opcode|funct|imm8>
//===----------------------------------------------------------------------===//
class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
@@ -303,13 +303,13 @@
MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
{
bits<3> func;
- bits<8> immed8;
+ bits<8> imm8;
let Opcode = op;
let func = _func;
let Inst{10-8} = func;
- let Inst{7-0} = immed8;
+ let Inst{7-0} = imm8;
}
//===----------------------------------------------------------------------===//
@@ -398,39 +398,39 @@
MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
{
bits<1> X;
- bits<26> immed26;
+ bits<26> imm26;
let X = _X;
let Inst{31-27} = 0b00011;
let Inst{26} = X;
- let Inst{25-21} = immed26{20-16};
- let Inst{20-16} = immed26{25-21};
- let Inst{15-0} = immed26{15-0};
+ let Inst{25-21} = imm26{20-16};
+ let Inst{20-16} = imm26{25-21};
+ let Inst{15-0} = imm26{15-0};
}
//===----------------------------------------------------------------------===//
// Format EXT-I instruction class in Mips16 :
-// <|opcode|immed10:5|immed15:1|op|0|0|0|0|0|0|immed4:0>
+// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
//===----------------------------------------------------------------------===//
class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
{
- bits<16> immed16;
+ bits<16> imm16;
bits<5> eop;
let eop = _eop;
- let Inst{26-21} = immed16{10-5};
- let Inst{20-16} = immed16{15-11};
+ let Inst{26-21} = imm16{10-5};
+ let Inst{20-16} = imm16{15-11};
let Inst{15-11} = eop;
let Inst{10-5} = 0;
- let Inst{4-0} = immed16{4-0};
+ let Inst{4-0} = imm16{4-0};
}
@@ -471,7 +471,7 @@
//===----------------------------------------------------------------------===//
// Format EXT-RI instruction class in Mips16 :
-// <|opcode|immed10:5|immed15:11|op|rx|0|0|0|immed4:0>
+// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
//===----------------------------------------------------------------------===//
class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
@@ -479,24 +479,24 @@
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
FrmEXT_RI16>
{
- bits<16> immed16;
+ bits<16> imm16;
bits<5> op;
bits<3> rx;
let op = _op;
- let Inst{26-21} = immed16{10-5};
- let Inst{20-16} = immed16{15-11};
+ let Inst{26-21} = imm16{10-5};
+ let Inst{20-16} = imm16{15-11};
let Inst{15-11} = op;
let Inst{10-8} = rx;
let Inst{7-5} = 0;
- let Inst{4-0} = immed16{4-0};
+ let Inst{4-0} = imm16{4-0};
}
//===----------------------------------------------------------------------===//
// Format EXT-RRI instruction class in Mips16 :
-// <|opcode|immed10:5|immed15:11|op|rx|ry|immed4:0>
+// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
//===----------------------------------------------------------------------===//
class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
@@ -504,23 +504,23 @@
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
FrmEXT_RRI16>
{
- bits<16> immed16;
+ bits<16> imm16;
bits<3> rx;
bits<3> ry;
- let Inst{26-21} = immed16{10-5};
- let Inst{20-16} = immed16{15-11};
+ let Inst{26-21} = imm16{10-5};
+ let Inst{20-16} = imm16{15-11};
let Inst{15-11} = _op;
let Inst{10-8} = rx;
let Inst{7-5} = ry;
- let Inst{4-0} = immed16{4-0};
+ let Inst{4-0} = imm16{4-0};
}
//===----------------------------------------------------------------------===//
// Format EXT-RRI-A instruction class in Mips16 :
-// <|opcode|immed10:4|immed14:11|RRI-A|rx|ry|f|immed3:0>
+// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
//===----------------------------------------------------------------------===//
class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
@@ -528,26 +528,26 @@
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
FrmEXT_RRI_A16>
{
- bits<15> immed15;
+ bits<15> imm15;
bits<3> rx;
bits<3> ry;
bits<1> f;
let f = _f;
- let Inst{26-20} = immed15{10-4};
- let Inst{19-16} = immed15{14-11};
+ let Inst{26-20} = imm15{10-4};
+ let Inst{19-16} = imm15{14-11};
let Inst{15-11} = 0b01000;
let Inst{10-8} = rx;
let Inst{7-5} = ry;
let Inst{4} = f;
- let Inst{3-0} = immed15{3-0};
+ let Inst{3-0} = imm15{3-0};
}
//===----------------------------------------------------------------------===//
// Format EXT-SHIFT instruction class in Mips16 :
-// <|opcode|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
+// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
//===----------------------------------------------------------------------===//
class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
@@ -575,7 +575,7 @@
//===----------------------------------------------------------------------===//
// Format EXT-I8 instruction class in Mips16 :
-// <|opcode|immed10:5|immed15:11|I8|funct|0|immed4:0>
+// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
//===----------------------------------------------------------------------===//
class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
@@ -583,24 +583,24 @@
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
FrmEXT_I816>
{
- bits<16> immed16;
+ bits<16> imm16;
bits<5> I8;
bits<3> funct;
let funct = _funct;
- let Inst{26-21} = immed16{10-5};
- let Inst{20-16} = immed16{15-11};
+ let Inst{26-21} = imm16{10-5};
+ let Inst{20-16} = imm16{15-11};
let Inst{15-11} = I8;
let Inst{10-8} = funct;
let Inst{7-5} = 0;
- let Inst{4-0} = immed16{4-0};
+ let Inst{4-0} = imm16{4-0};
}
//===----------------------------------------------------------------------===//
// Format EXT-I8_SVRS instruction class in Mips16 :
-// <|opcode|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
+// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
//===----------------------------------------------------------------------===//
class FEXT_I8_SVRS16<dag outs, dag ins, string asmstr,
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