[llvm-commits] [llvm] r157911 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/mem_update.ll test/CodeGen/PowerPC/stwu8.ll

[NAKAMURA Takumi]

Hal,

It has been causing failure.
Please try; llc -mtriple=powerpc-linux < test/CodeGen/Generic/APIntLoadStore.ll

XFAILed in r158209.

...Takumi


2012/6/4 Hal Finkel <hfinkel at anl.gov>:
> Author: hfinkel
> Date: Sun Jun  3 21:21:00 2012
> New Revision: 157911
>
> URL: http://llvm.org/viewvc/llvm-project?rev=157911&view=rev
> Log:
> Enable generating PPC pre-increment (r+imm) instructions by default.
>
> It seems that this no longer causes test suite failures on PPC64 (after r157159),
> and often gives a performance benefit, so it can be enabled by default.
>
> Modified:
>    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>    llvm/trunk/test/CodeGen/PowerPC/mem_update.ll
>    llvm/trunk/test/CodeGen/PowerPC/stwu8.ll
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=157911&r1=157910&r2=157911&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jun  3 21:21:00 2012
> @@ -51,9 +51,8 @@
>                                               ISD::ArgFlagsTy &ArgFlags,
>                                               CCState &State);
>
> -static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
> -cl::desc("enable preincrement load/store generation on PPC (experimental)"),
> -                                     cl::Hidden);
> +static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
> +cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
>
>  static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
>   if (TM.getSubtargetImpl()->isDarwin())
> @@ -1084,8 +1083,7 @@
>                                                   SDValue &Offset,
>                                                   ISD::MemIndexedMode &AM,
>                                                   SelectionDAG &DAG) const {
> -  // Disabled by default for now.
> -  if (!EnablePPCPreinc) return false;
> +  if (DisablePPCPreinc) return false;
>
>   SDValue Ptr;
>   EVT VT;
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/mem_update.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mem_update.ll?rev=157911&r1=157910&r2=157911&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/mem_update.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/mem_update.ll Sun Jun  3 21:21:00 2012
> @@ -1,6 +1,6 @@
> -; RUN: llc < %s -march=ppc32 -enable-ppc-preinc | \
> +; RUN: llc < %s -march=ppc32 | \
>  ; RUN:   not grep addi
> -; RUN: llc < %s -march=ppc64 -enable-ppc-preinc | \
> +; RUN: llc < %s -march=ppc64 | \
>  ; RUN:   not grep addi
>
>  @Glob = global i64 4
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/stwu8.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/stwu8.ll?rev=157911&r1=157910&r2=157911&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/stwu8.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/stwu8.ll Sun Jun  3 21:21:00 2012
> @@ -1,4 +1,4 @@
> -; RUN: llc -enable-ppc-preinc < %s | FileCheck %s
> +; RUN: llc < %s | FileCheck %s
>  target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
>  target triple = "powerpc64-unknown-linux-gnu"
>
>
>
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