[llvm-commits] [llvm] r157976 - in /llvm/trunk: include/llvm/Target/TargetSchedule.td lib/Target/X86/X86Schedule.td lib/Target/X86/X86ScheduleAtom.td

[Andrew Trick]

Author: atrick
Date: Mon Jun  4 22:44:29 2012
New Revision: 157976

URL: http://llvm.org/viewvc/llvm-project?rev=157976&view=rev
Log:
whitespace

Modified:
    llvm/trunk/include/llvm/Target/TargetSchedule.td
    llvm/trunk/lib/Target/X86/X86Schedule.td
    llvm/trunk/lib/Target/X86/X86ScheduleAtom.td

Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=157976&r1=157975&r2=157976&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td Mon Jun  4 22:44:29 2012
@@ -1,10 +1,10 @@
 //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the target-independent scheduling interfaces which should
@@ -19,7 +19,7 @@
 // all chip sets of the target.  Each functional unit is treated as a resource
 // during scheduling and has an affect instruction order based on availability
 // during a time interval.
-//  
+//
 class FuncUnit;
 
 //===----------------------------------------------------------------------===//
@@ -84,7 +84,7 @@
 def NoItinerary : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
-// Instruction itinerary data - These values provide a runtime map of an 
+// Instruction itinerary data - These values provide a runtime map of an
 // instruction itinerary class (name) to its itinerary data.
 //
 // OperandCycles are optional "cycle counts". They specify the cycle after
@@ -119,6 +119,7 @@
 //
 class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
                            list<InstrItinData> iid> {
+  int IssueWidth = 1;
   list<FuncUnit> FU = fu;
   list<Bypass> BP = bp;
   list<InstrItinData> IID = iid;

Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=157976&r1=157975&r2=157976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Mon Jun  4 22:44:29 2012
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// Instruction Itinerary classes used for X86 
+// Instruction Itinerary classes used for X86
 def IIC_DEFAULT     : InstrItinClass;
 def IIC_ALU_MEM     : InstrItinClass;
 def IIC_ALU_NONMEM  : InstrItinClass;
@@ -459,6 +459,3 @@
 def GenericItineraries : ProcessorItineraries<[], [], []>;
 
 include "X86ScheduleAtom.td"
-
-
-

Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=157976&r1=157975&r2=157976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Mon Jun  4 22:44:29 2012
@@ -106,7 +106,7 @@
   InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
   InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
   // set
-  InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, 
+  InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
   InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
   // jcc
   InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,