[llvm-commits] [llvm] r157937 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Akira Hatanaka ahatanaka at mips.com
Mon Jun 4 10:46:29 PDT 2012


Author: ahatanak
Date: Mon Jun  4 12:46:29 2012
New Revision: 157937

URL: http://llvm.org/viewvc/llvm-project?rev=157937&view=rev
Log:
Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
inserted after the shift-left-logical node.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=157937&r1=157936&r2=157937&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jun  4 12:46:29 2012
@@ -2144,7 +2144,8 @@
   DebugLoc DL = LD->getDebugLoc();
   SDValue Const32 = DAG.getConstant(32, MVT::i32);
   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
-  SDValue Ops[] = { SLL, LWR.getValue(1) };
+  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
+  SDValue Ops[] = { SRL, LWR.getValue(1) };
   return DAG.getMergeValues(Ops, 2, DL);
 }
 





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