[llvm-commits] [llvm] r156550 - in /llvm/trunk: lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/sub-cmp-peephole.ll

[Nick Lewycky]

Nick Lewycky wrote:
> Manman Ren wrote:
>> Author: mren
>> Date: Thu May 10 11:48:21 2012
>> New Revision: 156550
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=156550&view=rev
>> Log:
>> ARM: peephole optimization to remove cmp instruction
>>
>> This patch will optimize the following cases:
>>     sub r1, r3 | sub r1, imm
>>     cmp r3, r1 or cmp r1, r3 | cmp r1, imm
>>     bge L1
>>
>> TO
>>     subs r1, r3
>>     bge  L1 or ble L1
>>
>> If the branch instruction can use flag from "sub", then we can replace
>> "sub" with "subs" and eliminate the "cmp" instruction.
>>
>> rdar: 10734411
>>
>> Added:
>>       llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
>> Modified:
>>       llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
>>       llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>>

[...]

>> Added: llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll?rev=156550&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll (added)
>> +++ llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll Thu May 10 11:48:21 2012
>> @@ -0,0 +1,34 @@
>> +; RUN: llc<   %s -march=arm | FileCheck %s

Also, please add a -triple (-mtriple?) line to llc. The leading 
underscore in function names is optional based on the operating system.

Nick

>> +
>> +define i32 @f(i32 %a, i32 %b) nounwind ssp {
>> +entry:
>> +; CHECK: _f:
>> +; CHECK: subs
>> +; CHECK-NOT: cmp
>> +  %cmp = icmp sgt i32 %a, %b
>> +  %sub = sub nsw i32 %a, %b
>> +  %sub. = select i1 %cmp, i32 %sub, i32 0
>> +  ret i32 %sub.
>> +}
>> +
>> +define i32 @g(i32 %a, i32 %b) nounwind ssp {
>> +entry:
>> +; CHECK: _g:
>> +; CHECK: subs
>> +; CHECK-NOT: cmp
>> +  %cmp = icmp slt i32 %a, %b
>> +  %sub = sub nsw i32 %b, %a
>> +  %sub. = select i1 %cmp, i32 %sub, i32 0
>> +  ret i32 %sub.
>> +}
>> +
>> +define i32 @h(i32 %a, i32 %b) nounwind ssp {
>> +entry:
>> +; CHECK: _h:
>> +; CHECK: subs
>> +; CHECK-NOT: cmp
>> +  %cmp = icmp sgt i32 %a, 3
>> +  %sub = sub nsw i32 %a, 3
>> +  %sub. = select i1 %cmp, i32 %sub, i32 %b
>> +  ret i32 %sub.
>> +}
>>
>>
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>
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