[llvm-commits] [llvm] r156151 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h utils/TableGen/CodeGenRegisters.cpp utils/TableGen/CodeGenRegisters.h utils/TableGen/RegisterInfoEmitter.cpp
Evan Cheng
evan.cheng at apple.com
Mon May 7 18:02:03 PDT 2012
Nice!
Evan
On May 3, 2012, at 8:30 PM, Jakob Stoklund Olesen wrote:
> Author: stoklund
> Date: Thu May 3 22:30:28 2012
> New Revision: 156151
>
> URL: http://llvm.org/viewvc/llvm-project?rev=156151&view=rev
> Log:
> Remove TargetRegisterClass::SuperRegClasses.
>
> This manually enumerated list of super-register classes has been
> superceeded by the automatically computed super-register class masks
> available through SuperRegClassIterator.
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
> llvm/trunk/utils/TableGen/CodeGenRegisters.h
> llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=156151&r1=156150&r2=156151&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu May 3 22:30:28 2012
> @@ -45,7 +45,6 @@
> const uint32_t *SubClassMask;
> const uint16_t *SuperRegIndices;
> const sc_iterator SuperClasses;
> - const sc_iterator SuperRegClasses;
> ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
>
> /// getID() - Return the register class ID number.
> @@ -120,18 +119,6 @@
> return I;
> }
>
> - /// superregclasses_begin / superregclasses_end - Loop over all of
> - /// the superreg register classes of this register class.
> - sc_iterator superregclasses_begin() const {
> - return SuperRegClasses;
> - }
> -
> - sc_iterator superregclasses_end() const {
> - sc_iterator I = SuperRegClasses;
> - while (*I != NULL) ++I;
> - return I;
> - }
> -
> /// hasSubClass - return true if the specified TargetRegisterClass
> /// is a proper sub-class of this TargetRegisterClass.
> bool hasSubClass(const TargetRegisterClass *RC) const {
>
> Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=156151&r1=156150&r2=156151&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu May 3 22:30:28 2012
> @@ -505,29 +505,6 @@
> }
> }
>
> - // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
> - ListInit *SRC = R->getValueAsListInit("SubRegClasses");
> - for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
> - DagInit *DAG = dynamic_cast<DagInit*>(*i);
> - if (!DAG) throw "SubRegClasses must contain DAGs";
> - DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
> - Record *RCRec;
> - if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
> - throw "Operator '" + DAG->getOperator()->getAsString() +
> - "' in SubRegClasses is not a RegisterClass";
> - // Iterate over args, all SubRegIndex instances.
> - for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
> - ai != ae; ++ai) {
> - DefInit *Idx = dynamic_cast<DefInit*>(*ai);
> - Record *IdxRec;
> - if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
> - throw "Argument '" + (*ai)->getAsString() +
> - "' in SubRegClasses is not a SubRegIndex";
> - if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
> - throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
> - }
> - }
> -
> // Allow targets to override the size in bits of the RegisterClass.
> unsigned Size = R->getValueAsInt("Size");
>
>
> Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=156151&r1=156150&r2=156151&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)
> +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Thu May 3 22:30:28 2012
> @@ -197,8 +197,6 @@
> unsigned SpillAlignment;
> int CopyCost;
> bool Allocatable;
> - // Map SubRegIndex -> RegisterClass
> - DenseMap<Record*,Record*> SubRegClasses;
> std::string AltOrderSelect;
>
> // Return the Record that defined this class, or NULL if the class was
>
> Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=156151&r1=156150&r2=156151&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu May 3 22:30:28 2012
> @@ -776,58 +776,9 @@
>
> // Now that all of the structs have been emitted, emit the instances.
> if (!RegisterClasses.empty()) {
> - std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
> -
> OS << "\nstatic const TargetRegisterClass *const "
> << "NullRegClasses[] = { NULL };\n\n";
>
> - unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
> -
> - if (NumSubRegIndices) {
> - // Compute the super-register classes for each RegisterClass
> - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
> - const CodeGenRegisterClass &RC = *RegisterClasses[rc];
> - for (DenseMap<Record*,Record*>::const_iterator
> - i = RC.SubRegClasses.begin(),
> - e = RC.SubRegClasses.end(); i != e; ++i) {
> - // Find the register class number of i->second for SuperRegClassMap.
> - const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
> - assert(RC2 && "Invalid register class in SubRegClasses");
> - SuperRegClassMap[RC2->EnumValue].insert(rc);
> - }
> - }
> -
> - // Emit the super-register classes for each RegisterClass
> - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
> - const CodeGenRegisterClass &RC = *RegisterClasses[rc];
> -
> - // Give the register class a legal C name if it's anonymous.
> - std::string Name = RC.getName();
> -
> - OS << "// " << Name
> - << " Super-register Classes...\n"
> - << "static const TargetRegisterClass *const "
> - << Name << "SuperRegClasses[] = {\n ";
> -
> - bool Empty = true;
> - std::map<unsigned, std::set<unsigned> >::iterator I =
> - SuperRegClassMap.find(rc);
> - if (I != SuperRegClassMap.end()) {
> - for (std::set<unsigned>::iterator II = I->second.begin(),
> - EE = I->second.end(); II != EE; ++II) {
> - const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
> - if (!Empty)
> - OS << ", ";
> - OS << "&" << RC2.getQualifiedName() << "RegClass";
> - Empty = false;
> - }
> - }
> -
> - OS << (!Empty ? ", " : "") << "NULL";
> - OS << "\n};\n\n";
> - }
> - }
> -
> // Emit register class bit mask tables. The first bit mask emitted for a
> // register class, RC, is the set of sub-classes, including RC itself.
> //
> @@ -946,8 +897,6 @@
> OS << "NullRegClasses,\n ";
> else
> OS << RC.getName() << "Superclasses,\n ";
> - OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
> - << "RegClasses,\n ";
> if (RC.AltOrderSelect.empty())
> OS << "0\n";
> else
>
>
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