[llvm-commits] [llvm] r156278 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

[Eric Christopher]

Author: echristo
Date: Sun May  6 22:13:22 2012
New Revision: 156278

URL: http://llvm.org/viewvc/llvm-project?rev=156278&view=rev
Log:
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.

Patch by Jack Carter.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=156278&r1=156277&r2=156278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun May  6 22:13:22 2012
@@ -3056,8 +3056,10 @@
     case 'r':
       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
         return std::make_pair(0U, &Mips::CPURegsRegClass);
-      assert(VT == MVT::i64 && "Unexpected type.");
-      return std::make_pair(0U, &Mips::CPU64RegsRegClass);
+      if (VT == MVT::i64 && HasMips64)
+        return std::make_pair(0U, &Mips::CPU64RegsRegClass);
+      // This will generate an error message
+      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
     case 'f':
       if (VT == MVT::f32)
         return std::make_pair(0U, &Mips::FGR32RegClass);