[llvm-commits] [llvm] r156196 [1/2] - in /llvm/trunk: ./ autoconf/ include/llvm/ include/llvm/ADT/ lib/Support/ lib/Target/ lib/Target/NVPTX/ lib/Target/NVPTX/InstPrinter/ lib/Target/NVPTX/MCTargetDesc/ lib/Target/NVPTX/TargetInfo/ projects/sampl
Justin Holewinski
justin.holewinski at gmail.com
Fri May 4 17:45:20 PDT 2012
Thanks for the fixes! I was using Clang 3.0 as the main compiler. I'll
try to keep up with newer Clang builds to catch these.
On Fri, May 4, 2012 at 2:37 PM, Chandler Carruth <chandlerc at google.com>wrote:
> Just FYI, I fixed a warning in this code with r156209. You'll probably
> want to start using a bootstrapped Clang for builds so you get more of the
> warnings we care about with LLVM.
>
> Thanks for the great contribution.
>
> On Fri, May 4, 2012 at 1:18 PM, Justin Holewinski <jholewinski at nvidia.com>wrote:
>
>> Author: jholewinski
>> Date: Fri May 4 15:18:50 2012
>> New Revision: 156196
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=156196&view=rev
>> Log:
>> This patch adds a new NVPTX back-end to LLVM which supports code
>> generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the
>> current PTX back-end, while maintaining compatibility with it.
>>
>> The new target machines are:
>>
>> nvptx (old ptx32) => 32-bit PTX
>> nvptx64 (old ptx64) => 64-bit PTX
>>
>> The sources are based on the internal NVIDIA NVPTX back-end, and
>> contain more functionality than the current PTX back-end currently
>> provides.
>>
>> NV_CONTRIB
>>
>> Added:
>> llvm/trunk/include/llvm/IntrinsicsNVVM.td
>> llvm/trunk/lib/Target/NVPTX/
>> llvm/trunk/lib/Target/NVPTX/CMakeLists.txt
>> llvm/trunk/lib/Target/NVPTX/InstPrinter/
>> llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt
>> llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt
>> llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile
>> llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp
>> llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
>> llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h
>> llvm/trunk/lib/Target/NVPTX/Makefile
>> llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h
>> llvm/trunk/lib/Target/NVPTX/NVPTX.h
>> llvm/trunk/lib/Target/NVPTX/NVPTX.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXInstrFormats.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXIntrinsics.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXLowerAggrCopies.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXNumRegisters.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXSection.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXUtilities.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXUtilities.h
>> llvm/trunk/lib/Target/NVPTX/NVPTXVector.td
>> llvm/trunk/lib/Target/NVPTX/NVPTXutil.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXutil.h
>> llvm/trunk/lib/Target/NVPTX/TargetInfo/
>> llvm/trunk/lib/Target/NVPTX/TargetInfo/CMakeLists.txt
>> llvm/trunk/lib/Target/NVPTX/TargetInfo/LLVMBuild.txt
>> llvm/trunk/lib/Target/NVPTX/TargetInfo/Makefile
>> llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
>> llvm/trunk/lib/Target/NVPTX/VectorElementize.cpp
>> llvm/trunk/lib/Target/NVPTX/cl_common_defines.h
>> llvm/trunk/lib/Target/NVPTX/gen-register-defs.py
>> llvm/trunk/test/CodeGen/NVPTX/
>> llvm/trunk/test/CodeGen/NVPTX/annotations.ll
>> llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll
>> llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
>> llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll
>> llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll
>> llvm/trunk/test/CodeGen/NVPTX/compare-int.ll
>> llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll
>> llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll
>> llvm/trunk/test/CodeGen/NVPTX/convert-int-sm20.ll
>> llvm/trunk/test/CodeGen/NVPTX/fma-disable.ll
>> llvm/trunk/test/CodeGen/NVPTX/fma.ll
>> llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll
>> llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll
>> llvm/trunk/test/CodeGen/NVPTX/ld-generic.ll
>> llvm/trunk/test/CodeGen/NVPTX/lit.local.cfg
>> llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll
>> llvm/trunk/test/CodeGen/NVPTX/st-generic.ll
>> Modified:
>> llvm/trunk/CMakeLists.txt
>> llvm/trunk/autoconf/configure.ac
>> llvm/trunk/configure
>> llvm/trunk/include/llvm/ADT/Triple.h
>> llvm/trunk/include/llvm/Intrinsics.td
>> llvm/trunk/lib/Support/Triple.cpp
>> llvm/trunk/lib/Target/LLVMBuild.txt
>> llvm/trunk/projects/sample/autoconf/configure.ac
>> llvm/trunk/projects/sample/configure
>>
>> Modified: llvm/trunk/CMakeLists.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/CMakeLists.txt (original)
>> +++ llvm/trunk/CMakeLists.txt Fri May 4 15:18:50 2012
>> @@ -78,6 +78,7 @@
>> Mips
>> MBlaze
>> MSP430
>> + NVPTX
>> PowerPC
>> PTX
>> Sparc
>>
>> Modified: llvm/trunk/autoconf/configure.ac
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/autoconf/configure.ac (original)
>> +++ llvm/trunk/autoconf/configure.ac Fri May 4 15:18:50 2012
>> @@ -370,6 +370,7 @@
>> hexagon-*) llvm_cv_target_arch="Hexagon" ;;
>> mblaze-*) llvm_cv_target_arch="MBlaze" ;;
>> ptx-*) llvm_cv_target_arch="PTX" ;;
>> + nvptx-*) llvm_cv_target_arch="NVPTX" ;;
>> *) llvm_cv_target_arch="Unknown" ;;
>> esac])
>>
>> @@ -517,6 +518,7 @@
>> Hexagon) AC_SUBST(TARGET_HAS_JIT,0) ;;
>> MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;;
>> PTX) AC_SUBST(TARGET_HAS_JIT,0) ;;
>> + NVPTX) AC_SUBST(TARGET_HAS_JIT,0) ;;
>> *) AC_SUBST(TARGET_HAS_JIT,0) ;;
>> esac
>> fi
>> @@ -628,13 +630,13 @@
>> AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
>> [Build specific host targets: all or target1,target2,... Valid
>> targets are:
>> host, x86, x86_64, sparc, powerpc, arm, mips, spu, hexagon,
>> - xcore, msp430, ptx, and cpp (default=all)]),,
>> + xcore, msp430, ptx, nvptx, and cpp (default=all)]),,
>> enableval=all)
>> if test "$enableval" = host-only ; then
>> enableval=host
>> fi
>> case "$enableval" in
>> - all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430
>> CppBackend MBlaze PTX Hexagon" ;;
>> + all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430
>> CppBackend MBlaze PTX NVPTX Hexagon" ;;
>> *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
>> case "$a_target" in
>> x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> @@ -651,6 +653,7 @@
>> hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
>> mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
>> ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
>> + nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
>> host) case "$llvm_cv_target_arch" in
>> x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> @@ -664,6 +667,7 @@
>> MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
>> Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
>> PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
>> + NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
>> *) AC_MSG_ERROR([Can not set target to build]) ;;
>> esac ;;
>> *) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
>>
>> Modified: llvm/trunk/configure
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/configure (original)
>> +++ llvm/trunk/configure Fri May 4 15:18:50 2012
>> @@ -1420,7 +1420,7 @@
>> --enable-targets Build specific host targets: all or
>> target1,target2,... Valid targets are: host,
>> x86,
>> x86_64, sparc, powerpc, arm, mips, spu, hexagon,
>> - xcore, msp430, ptx, and cpp (default=all)
>> + xcore, msp430, ptx, nvptx, and cpp
>> (default=all)
>> --enable-bindings Build specific language bindings:
>> all,auto,none,{binding-name} (default=auto)
>> --enable-libffi Check for the presence of libffi (default is NO)
>> @@ -3903,6 +3903,7 @@
>> hexagon-*) llvm_cv_target_arch="Hexagon" ;;
>> mblaze-*) llvm_cv_target_arch="MBlaze" ;;
>> ptx-*) llvm_cv_target_arch="PTX" ;;
>> + nvptx-*) llvm_cv_target_arch="NVPTX" ;;
>> *) llvm_cv_target_arch="Unknown" ;;
>> esac
>> fi
>> @@ -5126,6 +5127,8 @@
>> ;;
>> PTX) TARGET_HAS_JIT=0
>> ;;
>> + NVPTX) TARGET_HAS_JIT=0
>> + ;;
>> *) TARGET_HAS_JIT=0
>> ;;
>> esac
>> @@ -5310,7 +5313,7 @@
>> enableval=host
>> fi
>> case "$enableval" in
>> - all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430
>> CppBackend MBlaze PTX Hexagon" ;;
>> + all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430
>> CppBackend MBlaze PTX NVPTX Hexagon" ;;
>> *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
>> case "$a_target" in
>> x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> @@ -5327,6 +5330,7 @@
>> hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
>> mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
>> ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
>> + nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
>> host) case "$llvm_cv_target_arch" in
>> x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
>> @@ -5340,6 +5344,7 @@
>> MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
>> Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
>> PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
>> + NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
>> *) { { echo "$as_me:$LINENO: error: Can not set target
>> to build" >&5
>> echo "$as_me: error: Can not set target to build" >&2;}
>> { (exit 1); exit 1; }; } ;;
>> @@ -10401,7 +10406,7 @@
>> lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
>> lt_status=$lt_dlunknown
>> cat > conftest.$ac_ext <<EOF
>> -#line 10404 "configure"
>> +#line 10409 "configure"
>> #include "confdefs.h"
>>
>> #if HAVE_DLFCN_H
>>
>> Modified: llvm/trunk/include/llvm/ADT/Triple.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/ADT/Triple.h (original)
>> +++ llvm/trunk/include/llvm/ADT/Triple.h Fri May 4 15:18:50 2012
>> @@ -64,6 +64,8 @@
>> mblaze, // MBlaze: mblaze
>> ptx32, // PTX: ptx (32-bit)
>> ptx64, // PTX: ptx (64-bit)
>> + nvptx, // NVPTX: 32-bit
>> + nvptx64, // NVPTX: 64-bit
>> le32, // le32: generic little-endian 32-bit CPU (PNaCl /
>> Emscripten)
>> amdil // amdil: amd IL
>> };
>>
>> Modified: llvm/trunk/include/llvm/Intrinsics.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/Intrinsics.td (original)
>> +++ llvm/trunk/include/llvm/Intrinsics.td Fri May 4 15:18:50 2012
>> @@ -441,3 +441,4 @@
>> include "llvm/IntrinsicsXCore.td"
>> include "llvm/IntrinsicsPTX.td"
>> include "llvm/IntrinsicsHexagon.td"
>> +include "llvm/IntrinsicsNVVM.td"
>>
>> Added: llvm/trunk/include/llvm/IntrinsicsNVVM.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsNVVM.td?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/IntrinsicsNVVM.td (added)
>> +++ llvm/trunk/include/llvm/IntrinsicsNVVM.td Fri May 4 15:18:50 2012
>> @@ -0,0 +1,872 @@
>> +//===- IntrinsicsNVVM.td - Defines NVVM intrinsics ---------*- tablegen
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file defines all of the NVVM-specific intrinsics for use with
>> NVPTX.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +def llvm_anyi64ptr_ty : LLVMAnyPointerType<llvm_i64_ty>; //
>> (space)i64*
>> +
>> +//
>> +// MISC
>> +//
>> +
>> + def int_nvvm_clz_i : GCCBuiltin<"__nvvm_clz_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_clz_ll : GCCBuiltin<"__nvvm_clz_ll">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_popc_i : GCCBuiltin<"__nvvm_popc_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_popc_ll : GCCBuiltin<"__nvvm_popc_ll">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_prmt : GCCBuiltin<"__nvvm_prmt">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Min Max
>> +//
>> +
>> + def int_nvvm_min_i : GCCBuiltin<"__nvvm_min_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_min_ui : GCCBuiltin<"__nvvm_min_ui">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_min_ll : GCCBuiltin<"__nvvm_min_ll">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_min_ull : GCCBuiltin<"__nvvm_min_ull">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_max_i : GCCBuiltin<"__nvvm_max_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_max_ui : GCCBuiltin<"__nvvm_max_ui">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_max_ll : GCCBuiltin<"__nvvm_max_ll">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_max_ull : GCCBuiltin<"__nvvm_max_ull">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_fmin_f : GCCBuiltin<"__nvvm_fmin_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fmin_ftz_f : GCCBuiltin<"__nvvm_fmin_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_fmax_f : GCCBuiltin<"__nvvm_fmax_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty]
>> + , [IntrNoMem, Commutative]>;
>> + def int_nvvm_fmax_ftz_f : GCCBuiltin<"__nvvm_fmax_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_fmin_d : GCCBuiltin<"__nvvm_fmin_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fmax_d : GCCBuiltin<"__nvvm_fmax_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Multiplication
>> +//
>> +
>> + def int_nvvm_mulhi_i : GCCBuiltin<"__nvvm_mulhi_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mulhi_ui : GCCBuiltin<"__nvvm_mulhi_ui">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_mulhi_ll : GCCBuiltin<"__nvvm_mulhi_ll">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mulhi_ull : GCCBuiltin<"__nvvm_mulhi_ull">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_mul_rn_ftz_f : GCCBuiltin<"__nvvm_mul_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rn_f : GCCBuiltin<"__nvvm_mul_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rz_ftz_f : GCCBuiltin<"__nvvm_mul_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rz_f : GCCBuiltin<"__nvvm_mul_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rm_ftz_f : GCCBuiltin<"__nvvm_mul_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rm_f : GCCBuiltin<"__nvvm_mul_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rp_ftz_f : GCCBuiltin<"__nvvm_mul_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rp_f : GCCBuiltin<"__nvvm_mul_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_mul_rn_d : GCCBuiltin<"__nvvm_mul_rn_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rz_d : GCCBuiltin<"__nvvm_mul_rz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rm_d : GCCBuiltin<"__nvvm_mul_rm_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul_rp_d : GCCBuiltin<"__nvvm_mul_rp_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_mul24_i : GCCBuiltin<"__nvvm_mul24_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_mul24_ui : GCCBuiltin<"__nvvm_mul24_ui">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Div
>> +//
>> +
>> + def int_nvvm_div_approx_ftz_f : GCCBuiltin<"__nvvm_div_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_approx_f : GCCBuiltin<"__nvvm_div_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_div_rn_ftz_f : GCCBuiltin<"__nvvm_div_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rn_f : GCCBuiltin<"__nvvm_div_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_div_rz_ftz_f : GCCBuiltin<"__nvvm_div_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rz_f : GCCBuiltin<"__nvvm_div_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_div_rm_ftz_f : GCCBuiltin<"__nvvm_div_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rm_f : GCCBuiltin<"__nvvm_div_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_div_rp_ftz_f : GCCBuiltin<"__nvvm_div_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rp_f : GCCBuiltin<"__nvvm_div_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_div_rn_d : GCCBuiltin<"__nvvm_div_rn_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rz_d : GCCBuiltin<"__nvvm_div_rz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rm_d : GCCBuiltin<"__nvvm_div_rm_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_div_rp_d : GCCBuiltin<"__nvvm_div_rp_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Brev
>> +//
>> +
>> + def int_nvvm_brev32 : GCCBuiltin<"__nvvm_brev32">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_brev64 : GCCBuiltin<"__nvvm_brev64">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Sad
>> +//
>> +
>> + def int_nvvm_sad_i : GCCBuiltin<"__nvvm_sad_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_sad_ui : GCCBuiltin<"__nvvm_sad_ui">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Floor Ceil
>> +//
>> +
>> + def int_nvvm_floor_ftz_f : GCCBuiltin<"__nvvm_floor_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_floor_f : GCCBuiltin<"__nvvm_floor_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_floor_d : GCCBuiltin<"__nvvm_floor_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_ceil_ftz_f : GCCBuiltin<"__nvvm_ceil_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_ceil_f : GCCBuiltin<"__nvvm_ceil_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_ceil_d : GCCBuiltin<"__nvvm_ceil_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Abs
>> +//
>> +
>> + def int_nvvm_abs_i : GCCBuiltin<"__nvvm_abs_i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_abs_ll : GCCBuiltin<"__nvvm_abs_ll">,
>> + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_fabs_ftz_f : GCCBuiltin<"__nvvm_fabs_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_fabs_f : GCCBuiltin<"__nvvm_fabs_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_fabs_d : GCCBuiltin<"__nvvm_fabs_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Round
>> +//
>> +
>> + def int_nvvm_round_ftz_f : GCCBuiltin<"__nvvm_round_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_round_f : GCCBuiltin<"__nvvm_round_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_round_d : GCCBuiltin<"__nvvm_round_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Trunc
>> +//
>> +
>> + def int_nvvm_trunc_ftz_f : GCCBuiltin<"__nvvm_trunc_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_trunc_f : GCCBuiltin<"__nvvm_trunc_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_trunc_d : GCCBuiltin<"__nvvm_trunc_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Saturate
>> +//
>> +
>> + def int_nvvm_saturate_ftz_f : GCCBuiltin<"__nvvm_saturate_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_saturate_f : GCCBuiltin<"__nvvm_saturate_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_saturate_d : GCCBuiltin<"__nvvm_saturate_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Exp2 Log2
>> +//
>> +
>> + def int_nvvm_ex2_approx_ftz_f : GCCBuiltin<"__nvvm_ex2_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_ex2_approx_f : GCCBuiltin<"__nvvm_ex2_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_ex2_approx_d : GCCBuiltin<"__nvvm_ex2_approx_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_lg2_approx_ftz_f : GCCBuiltin<"__nvvm_lg2_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_lg2_approx_f : GCCBuiltin<"__nvvm_lg2_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_lg2_approx_d : GCCBuiltin<"__nvvm_lg2_approx_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Sin Cos
>> +//
>> +
>> + def int_nvvm_sin_approx_ftz_f : GCCBuiltin<"__nvvm_sin_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sin_approx_f : GCCBuiltin<"__nvvm_sin_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_cos_approx_ftz_f : GCCBuiltin<"__nvvm_cos_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_cos_approx_f : GCCBuiltin<"__nvvm_cos_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Fma
>> +//
>> +
>> + def int_nvvm_fma_rn_ftz_f : GCCBuiltin<"__nvvm_fma_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rn_f : GCCBuiltin<"__nvvm_fma_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rz_ftz_f : GCCBuiltin<"__nvvm_fma_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rz_f : GCCBuiltin<"__nvvm_fma_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rm_ftz_f : GCCBuiltin<"__nvvm_fma_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rm_f : GCCBuiltin<"__nvvm_fma_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rp_ftz_f : GCCBuiltin<"__nvvm_fma_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rp_f : GCCBuiltin<"__nvvm_fma_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
>> llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_fma_rn_d : GCCBuiltin<"__nvvm_fma_rn_d">,
>> + Intrinsic<[llvm_double_ty],
>> + [llvm_double_ty, llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rz_d : GCCBuiltin<"__nvvm_fma_rz_d">,
>> + Intrinsic<[llvm_double_ty],
>> + [llvm_double_ty, llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rm_d : GCCBuiltin<"__nvvm_fma_rm_d">,
>> + Intrinsic<[llvm_double_ty],
>> + [llvm_double_ty, llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_fma_rp_d : GCCBuiltin<"__nvvm_fma_rp_d">,
>> + Intrinsic<[llvm_double_ty],
>> + [llvm_double_ty, llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Rcp
>> +//
>> +
>> + def int_nvvm_rcp_rn_ftz_f : GCCBuiltin<"__nvvm_rcp_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rn_f : GCCBuiltin<"__nvvm_rcp_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rz_ftz_f : GCCBuiltin<"__nvvm_rcp_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rz_f : GCCBuiltin<"__nvvm_rcp_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rm_ftz_f : GCCBuiltin<"__nvvm_rcp_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rm_f : GCCBuiltin<"__nvvm_rcp_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rp_ftz_f : GCCBuiltin<"__nvvm_rcp_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rp_f : GCCBuiltin<"__nvvm_rcp_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_rcp_rn_d : GCCBuiltin<"__nvvm_rcp_rn_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rz_d : GCCBuiltin<"__nvvm_rcp_rz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rm_d : GCCBuiltin<"__nvvm_rcp_rm_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_rcp_rp_d : GCCBuiltin<"__nvvm_rcp_rp_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_rcp_approx_ftz_d : GCCBuiltin<"__nvvm_rcp_approx_ftz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Sqrt
>> +//
>> +
>> + def int_nvvm_sqrt_rn_ftz_f : GCCBuiltin<"__nvvm_sqrt_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rn_f : GCCBuiltin<"__nvvm_sqrt_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rz_ftz_f : GCCBuiltin<"__nvvm_sqrt_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rz_f : GCCBuiltin<"__nvvm_sqrt_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rm_ftz_f : GCCBuiltin<"__nvvm_sqrt_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rm_f : GCCBuiltin<"__nvvm_sqrt_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rp_ftz_f : GCCBuiltin<"__nvvm_sqrt_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rp_f : GCCBuiltin<"__nvvm_sqrt_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_approx_ftz_f :
>> GCCBuiltin<"__nvvm_sqrt_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_approx_f : GCCBuiltin<"__nvvm_sqrt_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_sqrt_rn_d : GCCBuiltin<"__nvvm_sqrt_rn_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rz_d : GCCBuiltin<"__nvvm_sqrt_rz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rm_d : GCCBuiltin<"__nvvm_sqrt_rm_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_sqrt_rp_d : GCCBuiltin<"__nvvm_sqrt_rp_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Rsqrt
>> +//
>> +
>> + def int_nvvm_rsqrt_approx_ftz_f :
>> GCCBuiltin<"__nvvm_rsqrt_approx_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rsqrt_approx_f : GCCBuiltin<"__nvvm_rsqrt_approx_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_rsqrt_approx_d : GCCBuiltin<"__nvvm_rsqrt_approx_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Add
>> +//
>> +
>> + def int_nvvm_add_rn_ftz_f : GCCBuiltin<"__nvvm_add_rn_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rn_f : GCCBuiltin<"__nvvm_add_rn_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rz_ftz_f : GCCBuiltin<"__nvvm_add_rz_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rz_f : GCCBuiltin<"__nvvm_add_rz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rm_ftz_f : GCCBuiltin<"__nvvm_add_rm_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rm_f : GCCBuiltin<"__nvvm_add_rm_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rp_ftz_f : GCCBuiltin<"__nvvm_add_rp_ftz_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rp_f : GCCBuiltin<"__nvvm_add_rp_f">,
>> + Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_add_rn_d : GCCBuiltin<"__nvvm_add_rn_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rz_d : GCCBuiltin<"__nvvm_add_rz_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rm_d : GCCBuiltin<"__nvvm_add_rm_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> + def int_nvvm_add_rp_d : GCCBuiltin<"__nvvm_add_rp_d">,
>> + Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> +//
>> +// Convert
>> +//
>> +
>> + def int_nvvm_d2f_rn_ftz : GCCBuiltin<"__nvvm_d2f_rn_ftz">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rn : GCCBuiltin<"__nvvm_d2f_rn">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rz_ftz : GCCBuiltin<"__nvvm_d2f_rz_ftz">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rz : GCCBuiltin<"__nvvm_d2f_rz">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rm_ftz : GCCBuiltin<"__nvvm_d2f_rm_ftz">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rm : GCCBuiltin<"__nvvm_d2f_rm">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rp_ftz : GCCBuiltin<"__nvvm_d2f_rp_ftz">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2f_rp : GCCBuiltin<"__nvvm_d2f_rp">,
>> + Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_d2i_rn : GCCBuiltin<"__nvvm_d2i_rn">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2i_rz : GCCBuiltin<"__nvvm_d2i_rz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2i_rm : GCCBuiltin<"__nvvm_d2i_rm">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2i_rp : GCCBuiltin<"__nvvm_d2i_rp">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_d2ui_rn : GCCBuiltin<"__nvvm_d2ui_rn">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ui_rz : GCCBuiltin<"__nvvm_d2ui_rz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ui_rm : GCCBuiltin<"__nvvm_d2ui_rm">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ui_rp : GCCBuiltin<"__nvvm_d2ui_rp">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_i2d_rn : GCCBuiltin<"__nvvm_i2d_rn">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2d_rz : GCCBuiltin<"__nvvm_i2d_rz">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2d_rm : GCCBuiltin<"__nvvm_i2d_rm">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2d_rp : GCCBuiltin<"__nvvm_i2d_rp">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_ui2d_rn : GCCBuiltin<"__nvvm_ui2d_rn">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2d_rz : GCCBuiltin<"__nvvm_ui2d_rz">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2d_rm : GCCBuiltin<"__nvvm_ui2d_rm">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2d_rp : GCCBuiltin<"__nvvm_ui2d_rp">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_f2i_rn_ftz : GCCBuiltin<"__nvvm_f2i_rn_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rn : GCCBuiltin<"__nvvm_f2i_rn">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rz_ftz : GCCBuiltin<"__nvvm_f2i_rz_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rz : GCCBuiltin<"__nvvm_f2i_rz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rm_ftz : GCCBuiltin<"__nvvm_f2i_rm_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rm : GCCBuiltin<"__nvvm_f2i_rm">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rp_ftz : GCCBuiltin<"__nvvm_f2i_rp_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2i_rp : GCCBuiltin<"__nvvm_f2i_rp">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_f2ui_rn_ftz : GCCBuiltin<"__nvvm_f2ui_rn_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rn : GCCBuiltin<"__nvvm_f2ui_rn">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rz_ftz : GCCBuiltin<"__nvvm_f2ui_rz_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rz : GCCBuiltin<"__nvvm_f2ui_rz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rm_ftz : GCCBuiltin<"__nvvm_f2ui_rm_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rm : GCCBuiltin<"__nvvm_f2ui_rm">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rp_ftz : GCCBuiltin<"__nvvm_f2ui_rp_ftz">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ui_rp : GCCBuiltin<"__nvvm_f2ui_rp">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_i2f_rn : GCCBuiltin<"__nvvm_i2f_rn">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2f_rz : GCCBuiltin<"__nvvm_i2f_rz">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2f_rm : GCCBuiltin<"__nvvm_i2f_rm">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_i2f_rp : GCCBuiltin<"__nvvm_i2f_rp">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_ui2f_rn : GCCBuiltin<"__nvvm_ui2f_rn">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2f_rz : GCCBuiltin<"__nvvm_ui2f_rz">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2f_rm : GCCBuiltin<"__nvvm_ui2f_rm">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> + def int_nvvm_ui2f_rp : GCCBuiltin<"__nvvm_ui2f_rp">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_lohi_i2d : GCCBuiltin<"__nvvm_lohi_i2d">,
>> + Intrinsic<[llvm_double_ty], [llvm_i32_ty, llvm_i32_ty],
>> + [IntrNoMem, Commutative]>;
>> +
>> + def int_nvvm_d2i_lo : GCCBuiltin<"__nvvm_d2i_lo">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2i_hi : GCCBuiltin<"__nvvm_d2i_hi">,
>> + Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_f2ll_rn_ftz : GCCBuiltin<"__nvvm_f2ll_rn_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rn : GCCBuiltin<"__nvvm_f2ll_rn">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rz_ftz : GCCBuiltin<"__nvvm_f2ll_rz_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rz : GCCBuiltin<"__nvvm_f2ll_rz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rm_ftz : GCCBuiltin<"__nvvm_f2ll_rm_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rm : GCCBuiltin<"__nvvm_f2ll_rm">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rp_ftz : GCCBuiltin<"__nvvm_f2ll_rp_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ll_rp : GCCBuiltin<"__nvvm_f2ll_rp">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_f2ull_rn_ftz : GCCBuiltin<"__nvvm_f2ull_rn_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rn : GCCBuiltin<"__nvvm_f2ull_rn">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rz_ftz : GCCBuiltin<"__nvvm_f2ull_rz_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rz : GCCBuiltin<"__nvvm_f2ull_rz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rm_ftz : GCCBuiltin<"__nvvm_f2ull_rm_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rm : GCCBuiltin<"__nvvm_f2ull_rm">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rp_ftz : GCCBuiltin<"__nvvm_f2ull_rp_ftz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2ull_rp : GCCBuiltin<"__nvvm_f2ull_rp">,
>> + Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_d2ll_rn : GCCBuiltin<"__nvvm_d2ll_rn">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ll_rz : GCCBuiltin<"__nvvm_d2ll_rz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ll_rm : GCCBuiltin<"__nvvm_d2ll_rm">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ll_rp : GCCBuiltin<"__nvvm_d2ll_rp">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_d2ull_rn : GCCBuiltin<"__nvvm_d2ull_rn">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ull_rz : GCCBuiltin<"__nvvm_d2ull_rz">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ull_rm : GCCBuiltin<"__nvvm_d2ull_rm">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> + def int_nvvm_d2ull_rp : GCCBuiltin<"__nvvm_d2ull_rp">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_ll2f_rn : GCCBuiltin<"__nvvm_ll2f_rn">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2f_rz : GCCBuiltin<"__nvvm_ll2f_rz">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2f_rm : GCCBuiltin<"__nvvm_ll2f_rm">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2f_rp : GCCBuiltin<"__nvvm_ll2f_rp">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2f_rn : GCCBuiltin<"__nvvm_ull2f_rn">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2f_rz : GCCBuiltin<"__nvvm_ull2f_rz">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2f_rm : GCCBuiltin<"__nvvm_ull2f_rm">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2f_rp : GCCBuiltin<"__nvvm_ull2f_rp">,
>> + Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_ll2d_rn : GCCBuiltin<"__nvvm_ll2d_rn">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2d_rz : GCCBuiltin<"__nvvm_ll2d_rz">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2d_rm : GCCBuiltin<"__nvvm_ll2d_rm">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ll2d_rp : GCCBuiltin<"__nvvm_ll2d_rp">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2d_rn : GCCBuiltin<"__nvvm_ull2d_rn">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2d_rz : GCCBuiltin<"__nvvm_ull2d_rz">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2d_rm : GCCBuiltin<"__nvvm_ull2d_rm">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_ull2d_rp : GCCBuiltin<"__nvvm_ull2d_rp">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_f2h_rn_ftz : GCCBuiltin<"__nvvm_f2h_rn_ftz">,
>> + Intrinsic<[llvm_i16_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_f2h_rn : GCCBuiltin<"__nvvm_f2h_rn">,
>> + Intrinsic<[llvm_i16_ty], [llvm_float_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_h2f : GCCBuiltin<"__nvvm_h2f">,
>> + Intrinsic<[llvm_float_ty], [llvm_i16_ty], [IntrNoMem]>;
>> +
>> +//
>> +// Bitcast
>> +//
>> +
>> + def int_nvvm_bitcast_f2i : GCCBuiltin<"__nvvm_bitcast_f2i">,
>> + Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
>> + def int_nvvm_bitcast_i2f : GCCBuiltin<"__nvvm_bitcast_i2f">,
>> + Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
>> +
>> + def int_nvvm_bitcast_ll2d : GCCBuiltin<"__nvvm_bitcast_ll2d">,
>> + Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;
>> + def int_nvvm_bitcast_d2ll : GCCBuiltin<"__nvvm_bitcast_d2ll">,
>> + Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
>> +
>> +
>> +// Atomic not available as an llvm intrinsic.
>> + def int_nvvm_atomic_load_add_f32 : Intrinsic<[llvm_float_ty],
>> + [LLVMAnyPointerType<llvm_float_ty>, llvm_float_ty],
>> + [IntrReadWriteArgMem,
>> NoCapture<0>]>;
>> + def int_nvvm_atomic_load_inc_32 : Intrinsic<[llvm_i32_ty],
>> + [LLVMAnyPointerType<llvm_i32_ty>, llvm_i32_ty],
>> + [IntrReadWriteArgMem,
>> NoCapture<0>]>;
>> + def int_nvvm_atomic_load_dec_32 : Intrinsic<[llvm_i32_ty],
>> + [LLVMAnyPointerType<llvm_i32_ty>, llvm_i32_ty],
>> + [IntrReadWriteArgMem,
>> NoCapture<0>]>;
>> +
>> +// Bar.Sync
>> + def int_cuda_syncthreads : GCCBuiltin<"__syncthreads">,
>> + Intrinsic<[], [], []>;
>> + def int_nvvm_barrier0 : GCCBuiltin<"__nvvm_bar0">,
>> + Intrinsic<[], [], []>;
>> + def int_nvvm_barrier0_popc : GCCBuiltin<"__nvvm_bar0_popc">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
>> + def int_nvvm_barrier0_and : GCCBuiltin<"__nvvm_bar0_and">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
>> + def int_nvvm_barrier0_or : GCCBuiltin<"__nvvm_bar0_or">,
>> + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
>> +
>> + // Membar
>> + def int_nvvm_membar_cta : GCCBuiltin<"__nvvm_membar_cta">,
>> + Intrinsic<[], [], []>;
>> + def int_nvvm_membar_gl : GCCBuiltin<"__nvvm_membar_gl">,
>> + Intrinsic<[], [], []>;
>> + def int_nvvm_membar_sys : GCCBuiltin<"__nvvm_membar_sys">,
>> + Intrinsic<[], [], []>;
>> +
>> +
>> +// Accessing special registers
>> + def int_nvvm_read_ptx_sreg_tid_x :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_tid_x">;
>> + def int_nvvm_read_ptx_sreg_tid_y :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_tid_y">;
>> + def int_nvvm_read_ptx_sreg_tid_z :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_tid_z">;
>> +
>> + def int_nvvm_read_ptx_sreg_ntid_x :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_x">;
>> + def int_nvvm_read_ptx_sreg_ntid_y :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_y">;
>> + def int_nvvm_read_ptx_sreg_ntid_z :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_z">;
>> +
>> + def int_nvvm_read_ptx_sreg_ctaid_x :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_x">;
>> + def int_nvvm_read_ptx_sreg_ctaid_y :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_y">;
>> + def int_nvvm_read_ptx_sreg_ctaid_z :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_z">;
>> +
>> + def int_nvvm_read_ptx_sreg_nctaid_x :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_x">;
>> + def int_nvvm_read_ptx_sreg_nctaid_y :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_y">;
>> + def int_nvvm_read_ptx_sreg_nctaid_z :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_z">;
>> +
>> + def int_nvvm_read_ptx_sreg_warpsize :
>> + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
>> + GCCBuiltin<"__nvvm_read_ptx_sreg_warpsize">;
>> +
>> +
>> +// Generated within nvvm. Use for ldu on sm_20 or later
>> +// @TODO: Revisit this, Changed LLVMAnyPointerType to LLVMPointerType
>> +def int_nvvm_ldu_global_i : Intrinsic<[llvm_anyint_ty],
>> + [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],
>> + "llvm.nvvm.ldu.global.i">;
>> +def int_nvvm_ldu_global_f : Intrinsic<[llvm_anyfloat_ty],
>> + [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],
>> + "llvm.nvvm.ldu.global.f">;
>> +def int_nvvm_ldu_global_p : Intrinsic<[llvm_anyptr_ty],
>> + [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],
>> + "llvm.nvvm.ldu.global.p">;
>> +
>> +
>> +// Use for generic pointers
>> +// - These intrinsics are used to convert address spaces.
>> +// - The input pointer and output pointer must have the same type,
>> except for
>> +// the address-space. (This restriction is not enforced here as there
>> is
>> +// currently no way to describe it).
>> +// - This complements the llvm bitcast, which can be used to cast one
>> type
>> +// of pointer to another type of pointer, while the address space
>> remains
>> +// the same.
>> +def int_nvvm_ptr_local_to_gen: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.local.to.gen">;
>> +def int_nvvm_ptr_shared_to_gen: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.shared.to.gen">;
>> +def int_nvvm_ptr_global_to_gen: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.global.to.gen">;
>> +def int_nvvm_ptr_constant_to_gen: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.constant.to.gen">;
>> +
>> +def int_nvvm_ptr_gen_to_global: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.gen.to.global">;
>> +def int_nvvm_ptr_gen_to_shared: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.gen.to.shared">;
>> +def int_nvvm_ptr_gen_to_local: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.gen.to.local">;
>> +def int_nvvm_ptr_gen_to_constant: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.gen.to.constant">;
>> +
>> +// Used in nvvm internally to help address space opt and ptx code
>> generation
>> +// This is for params that are passed to kernel functions by pointer
>> by-val.
>> +def int_nvvm_ptr_gen_to_param: Intrinsic<[llvm_anyptr_ty],
>> + [llvm_anyptr_ty],
>> + [IntrNoMem, NoCapture<0>],
>> + "llvm.nvvm.ptr.gen.to.param">;
>> +
>> +// Move intrinsics, used in nvvm internally
>> +
>> +def int_nvvm_move_i8 : Intrinsic<[llvm_i8_ty], [llvm_i8_ty], [IntrNoMem],
>> + "llvm.nvvm.move.i8">;
>> +def int_nvvm_move_i16 : Intrinsic<[llvm_i16_ty], [llvm_i16_ty],
>> [IntrNoMem],
>> + "llvm.nvvm.move.i16">;
>> +def int_nvvm_move_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
>> [IntrNoMem],
>> + "llvm.nvvm.move.i32">;
>> +def int_nvvm_move_i64 : Intrinsic<[llvm_i64_ty], [llvm_i64_ty],
>> [IntrNoMem],
>> + "llvm.nvvm.move.i64">;
>> +def int_nvvm_move_float : Intrinsic<[llvm_float_ty], [llvm_float_ty],
>> + [IntrNoMem], "llvm.nvvm.move.float">;
>> +def int_nvvm_move_double : Intrinsic<[llvm_double_ty], [llvm_double_ty],
>> + [IntrNoMem], "llvm.nvvm.move.double">;
>> +def int_nvvm_move_ptr : Intrinsic<[llvm_anyptr_ty], [llvm_anyptr_ty],
>> + [IntrNoMem, NoCapture<0>], "llvm.nvvm.move.ptr">;
>> +
>> +
>> +/// Error / Warn
>> +def int_nvvm_compiler_error :
>> + Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.error">;
>> +def int_nvvm_compiler_warn :
>> + Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.warn">;
>>
>> Modified: llvm/trunk/lib/Support/Triple.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Support/Triple.cpp (original)
>> +++ llvm/trunk/lib/Support/Triple.cpp Fri May 4 15:18:50 2012
>> @@ -40,6 +40,8 @@
>> case mblaze: return "mblaze";
>> case ptx32: return "ptx32";
>> case ptx64: return "ptx64";
>> + case nvptx: return "nvptx";
>> + case nvptx64: return "nvptx64";
>> case le32: return "le32";
>> case amdil: return "amdil";
>> }
>> @@ -76,6 +78,8 @@
>>
>> case ptx32: return "ptx";
>> case ptx64: return "ptx";
>> + case nvptx: return "nvptx";
>> + case nvptx64: return "nvptx";
>> case le32: return "le32";
>> case amdil: return "amdil";
>> }
>> @@ -162,6 +166,8 @@
>> .Case("xcore", xcore)
>> .Case("ptx32", ptx32)
>> .Case("ptx64", ptx64)
>> + .Case("nvptx", nvptx)
>> + .Case("nvptx64", nvptx64)
>> .Case("le32", le32)
>> .Case("amdil", amdil)
>> .Default(UnknownArch);
>> @@ -194,6 +200,8 @@
>> .Case("r600", Triple::r600)
>> .Case("ptx32", Triple::ptx32)
>> .Case("ptx64", Triple::ptx64)
>> + .Case("nvptx", Triple::nvptx)
>> + .Case("nvptx64", Triple::nvptx64)
>> .Case("amdil", Triple::amdil)
>> .Default(Triple::UnknownArch);
>> }
>> @@ -217,6 +225,8 @@
>> .Case("r600", "r600")
>> .Case("ptx32", "ptx32")
>> .Case("ptx64", "ptx64")
>> + .Case("nvptx", "nvptx")
>> + .Case("nvptx64", "nvptx64")
>> .Case("le32", "le32")
>> .Case("amdil", "amdil")
>> .Default(NULL);
>> @@ -251,6 +261,8 @@
>> .Case("xcore", Triple::xcore)
>> .Case("ptx32", Triple::ptx32)
>> .Case("ptx64", Triple::ptx64)
>> + .Case("nvptx", Triple::nvptx)
>> + .Case("nvptx64", Triple::nvptx64)
>> .Case("le32", Triple::le32)
>> .Case("amdil", Triple::amdil)
>> .Default(Triple::UnknownArch);
>> @@ -652,6 +664,7 @@
>> case llvm::Triple::mblaze:
>> case llvm::Triple::mips:
>> case llvm::Triple::mipsel:
>> + case llvm::Triple::nvptx:
>> case llvm::Triple::ppc:
>> case llvm::Triple::ptx32:
>> case llvm::Triple::r600:
>> @@ -664,6 +677,7 @@
>>
>> case llvm::Triple::mips64:
>> case llvm::Triple::mips64el:
>> + case llvm::Triple::nvptx64:
>> case llvm::Triple::ppc64:
>> case llvm::Triple::ptx64:
>> case llvm::Triple::sparcv9:
>> @@ -701,6 +715,7 @@
>> case Triple::mblaze:
>> case Triple::mips:
>> case Triple::mipsel:
>> + case Triple::nvptx:
>> case Triple::ppc:
>> case Triple::ptx32:
>> case Triple::r600:
>> @@ -714,6 +729,7 @@
>>
>> case Triple::mips64: T.setArch(Triple::mips); break;
>> case Triple::mips64el: T.setArch(Triple::mipsel); break;
>> + case Triple::nvptx64: T.setArch(Triple::nvptx); break;
>> case Triple::ppc64: T.setArch(Triple::ppc); break;
>> case Triple::ptx64: T.setArch(Triple::ptx32); break;
>> case Triple::sparcv9: T.setArch(Triple::sparc); break;
>> @@ -742,6 +758,7 @@
>>
>> case Triple::mips64:
>> case Triple::mips64el:
>> + case Triple::nvptx64:
>> case Triple::ppc64:
>> case Triple::ptx64:
>> case Triple::sparcv9:
>> @@ -751,6 +768,7 @@
>>
>> case Triple::mips: T.setArch(Triple::mips64); break;
>> case Triple::mipsel: T.setArch(Triple::mips64el); break;
>> + case Triple::nvptx: T.setArch(Triple::nvptx64); break;
>> case Triple::ppc: T.setArch(Triple::ppc64); break;
>> case Triple::ptx32: T.setArch(Triple::ptx64); break;
>> case Triple::sparc: T.setArch(Triple::sparcv9); break;
>>
>> Modified: llvm/trunk/lib/Target/LLVMBuild.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=156196&r1=156195&r2=156196&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/LLVMBuild.txt (original)
>> +++ llvm/trunk/lib/Target/LLVMBuild.txt Fri May 4 15:18:50 2012
>> @@ -16,7 +16,7 @@
>>
>> ;===------------------------------------------------------------------------===;
>>
>> [common]
>> -subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 Mips PTX
>> PowerPC Sparc X86 XCore
>> +subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips
>> PTX PowerPC Sparc X86 XCore
>>
>> ; This is a special group whose required libraries are extended (by
>> llvm-build)
>> ; with the best execution engine (the native JIT, if available, or the
>>
>> Added: llvm/trunk/lib/Target/NVPTX/CMakeLists.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/CMakeLists.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/CMakeLists.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/CMakeLists.txt Fri May 4 15:18:50 2012
>> @@ -0,0 +1,33 @@
>> +set(LLVM_TARGET_DEFINITIONS NVPTX.td)
>> +
>> +
>> +tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
>> +tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
>> +tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)
>> +tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)
>> +tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
>> +add_public_tablegen_target(NVPTXCommonTableGen)
>> +
>> +set(NVPTXCodeGen_sources
>> + NVPTXFrameLowering.cpp
>> + NVPTXInstrInfo.cpp
>> + NVPTXISelDAGToDAG.cpp
>> + NVPTXISelLowering.cpp
>> + NVPTXRegisterInfo.cpp
>> + NVPTXSubtarget.cpp
>> + NVPTXTargetMachine.cpp
>> + NVPTXSplitBBatBar.cpp
>> + NVPTXLowerAggrCopies.cpp
>> + NVPTXutil.cpp
>> + NVPTXAllocaHoisting.cpp
>> + NVPTXAsmPrinter.cpp
>> + NVPTXUtilities.cpp
>> + VectorElementize.cpp
>> + )
>> +
>> +add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources})
>> +
>> +
>> +add_subdirectory(TargetInfo)
>> +add_subdirectory(InstPrinter)
>> +add_subdirectory(MCTargetDesc)
>>
>> Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,7 @@
>> +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/..
>> ${CMAKE_CURRENT_SOURCE_DIR}/.. )
>> +
>> +add_llvm_library(LLVMNVPTXAsmPrinter
>> + NVPTXInstPrinter.cpp
>> + )
>> +
>> +add_dependencies(LLVMNVPTXAsmPrinter NVPTXCommonTableGen)
>>
>> Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,23 @@
>> +;===- ./lib/Target/NVPTX/InstPrinter/LLVMBuild.txt -------------*- Conf
>> -*--===;
>> +;
>> +; The LLVM Compiler Infrastructure
>> +;
>> +; This file is distributed under the University of Illinois Open Source
>> +; License. See LICENSE.TXT for details.
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +;
>> +; This is an LLVMBuild description file for the components in this
>> subdirectory.
>> +;
>> +; For more information on the LLVMBuild system, please see:
>> +;
>> +; http://llvm.org/docs/LLVMBuild.html
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +
>> +[component_0]
>> +type = Library
>> +name = NVPTXAsmPrinter
>> +parent = NVPTX
>> +required_libraries = MC Support
>> +add_to_library_groups = NVPTX
>>
>> Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile (added)
>> +++ llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile Fri May 4 15:18:50
>> 2012
>> @@ -0,0 +1,15 @@
>> +##===- lib/Target/NVPTX/AsmPrinter/Makefile ----------------*- Makefile
>> -*-===##
>> +#
>> +#
>> The LLVM Compiler Infrastructure
>> +#
>> +# This file is distributed under the University of Illinois Open Source
>> +# License. See LICENSE.TXT for details.
>> +#
>>
>> +##===----------------------------------------------------------------------===##
>> +LEVEL = ../../../..
>> +LIBRARYNAME = LLVMNVPTXAsmPrinter
>> +
>> +# Hack: we need to include 'main' ptx target directory to grab private
>> headers
>> +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
>> +
>> +include $(LEVEL)/Makefile.common
>>
>> Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp (added)
>> +++ llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp Fri May
>> 4 15:18:50 2012
>> @@ -0,0 +1 @@
>> +// Placeholder
>>
>> Added: llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt Fri May 4 15:18:50 2012
>> @@ -0,0 +1,32 @@
>> +;===- ./lib/Target/NVPTX/LLVMBuild.txt -------------------------*- Conf
>> -*--===;
>> +;
>> +; The LLVM Compiler Infrastructure
>> +;
>> +; This file is distributed under the University of Illinois Open Source
>> +; License. See LICENSE.TXT for details.
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +;
>> +; This is an LLVMBuild description file for the components in this
>> subdirectory.
>> +;
>> +; For more information on the LLVMBuild system, please see:
>> +;
>> +; http://llvm.org/docs/LLVMBuild.html
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +
>> +[common]
>> +subdirectories = InstPrinter MCTargetDesc TargetInfo
>> +
>> +[component_0]
>> +type = TargetGroup
>> +name = NVPTX
>> +parent = Target
>> +has_asmprinter = 1
>> +
>> +[component_1]
>> +type = Library
>> +name = NVPTXCodeGen
>> +parent = NVPTX
>> +required_libraries = Analysis AsmPrinter CodeGen Core MC NVPTXDesc
>> NVPTXInfo SelectionDAG Support Target TransformUtils
>> +add_to_library_groups = NVPTX
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,9 @@
>> +add_llvm_library(LLVMNVPTXDesc
>> + NVPTXMCAsmInfo.cpp
>> + NVPTXMCTargetDesc.cpp
>> + )
>> +
>> +add_dependencies(LLVMNVPTXDesc NVPTXCommonTableGen)
>> +
>> +# Hack: we need to include 'main' target directory to grab private
>> headers
>> +#include_directories(${CMAKE_CURRENT_SOURCE_DIR}/..
>> ${CMAKE_CURRENT_BINARY_DIR}/..)
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,23 @@
>> +;===- ./lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt ------------*- Conf
>> -*--===;
>> +;
>> +; The LLVM Compiler Infrastructure
>> +;
>> +; This file is distributed under the University of Illinois Open Source
>> +; License. See LICENSE.TXT for details.
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +;
>> +; This is an LLVMBuild description file for the components in this
>> subdirectory.
>> +;
>> +; For more information on the LLVMBuild system, please see:
>> +;
>> +; http://llvm.org/docs/LLVMBuild.html
>> +;
>>
>> +;===------------------------------------------------------------------------===;
>> +
>> +[component_0]
>> +type = Library
>> +name = NVPTXDesc
>> +parent = NVPTX
>> +required_libraries = MC NVPTXAsmPrinter NVPTXInfo Support
>> +add_to_library_groups = NVPTX
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile Fri May 4 15:18:50
>> 2012
>> @@ -0,0 +1,16 @@
>> +##===- lib/Target/NVPTX/TargetDesc/Makefile ----------------*- Makefile
>> -*-===##
>> +#
>> +# The LLVM Compiler Infrastructure
>> +#
>> +# This file is distributed under the University of Illinois Open Source
>> +# License. See LICENSE.TXT for details.
>> +#
>>
>> +##===----------------------------------------------------------------------===##
>> +
>> +LEVEL = ../../../..
>> +LIBRARYNAME = LLVMNVPTXDesc
>> +
>> +# Hack: we need to include 'main' target directory to grab private
>> headers
>> +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
>> +
>> +include $(LEVEL)/Makefile.common
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,88 @@
>> +//===-- NVPTXBaseInfo.h - Top-level definitions for NVPTX -------*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file contains small standalone helper functions and enum
>> definitions for
>> +// the NVPTX target useful for the compiler back-end and the MC
>> libraries.
>> +// As such, it deliberately does not include references to LLVM core
>> +// code gen types, passes, etc..
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#ifndef NVPTXBASEINFO_H
>> +#define NVPTXBASEINFO_H
>> +
>> +namespace llvm {
>> +
>> +enum AddressSpace {
>> + ADDRESS_SPACE_GENERIC = 0,
>> + ADDRESS_SPACE_GLOBAL = 1,
>> + ADDRESS_SPACE_CONST_NOT_GEN = 2, // Not part of generic space
>> + ADDRESS_SPACE_SHARED = 3,
>> + ADDRESS_SPACE_CONST = 4,
>> + ADDRESS_SPACE_LOCAL = 5,
>> +
>> + // NVVM Internal
>> + ADDRESS_SPACE_PARAM = 101
>> +};
>> +
>> +enum PropertyAnnotation {
>> + PROPERTY_MAXNTID_X = 0,
>> + PROPERTY_MAXNTID_Y,
>> + PROPERTY_MAXNTID_Z,
>> + PROPERTY_REQNTID_X,
>> + PROPERTY_REQNTID_Y,
>> + PROPERTY_REQNTID_Z,
>> + PROPERTY_MINNCTAPERSM,
>> + PROPERTY_ISTEXTURE,
>> + PROPERTY_ISSURFACE,
>> + PROPERTY_ISSAMPLER,
>> + PROPERTY_ISREADONLY_IMAGE_PARAM,
>> + PROPERTY_ISWRITEONLY_IMAGE_PARAM,
>> + PROPERTY_ISKERNEL_FUNCTION,
>> + PROPERTY_ALIGN,
>> +
>> + // last property
>> + PROPERTY_LAST
>> +};
>> +
>> +const unsigned AnnotationNameLen = 8; // length of each annotation name
>> +const char
>> +PropertyAnnotationNames[PROPERTY_LAST + 1][AnnotationNameLen + 1] = {
>> + "maxntidx", // PROPERTY_MAXNTID_X
>> + "maxntidy", // PROPERTY_MAXNTID_Y
>> + "maxntidz", // PROPERTY_MAXNTID_Z
>> + "reqntidx", // PROPERTY_REQNTID_X
>> + "reqntidy", // PROPERTY_REQNTID_Y
>> + "reqntidz", // PROPERTY_REQNTID_Z
>> + "minctasm", // PROPERTY_MINNCTAPERSM
>> + "texture", // PROPERTY_ISTEXTURE
>> + "surface", // PROPERTY_ISSURFACE
>> + "sampler", // PROPERTY_ISSAMPLER
>> + "rdoimage", // PROPERTY_ISREADONLY_IMAGE_PARAM
>> + "wroimage", // PROPERTY_ISWRITEONLY_IMAGE_PARAM
>> + "kernel", // PROPERTY_ISKERNEL_FUNCTION
>> + "align", // PROPERTY_ALIGN
>> +
>> + // last property
>> + "proplast", // PROPERTY_LAST
>> +};
>> +
>> +// name of named metadata used for global annotations
>> +#if defined(__GNUC__)
>> +// As this is declared to be static but some of the .cpp files that
>> +// include NVVM.h do not use this array, gcc gives a warning when
>> +// compiling those .cpp files, hence __attribute__((unused)).
>> +__attribute__((unused))
>> +#endif
>> +static const char* NamedMDForAnnotations = "nvvm.annotations";
>> +
>> +}
>> +
>> +
>> +#endif
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp Fri May
>> 4 15:18:50 2012
>> @@ -0,0 +1,63 @@
>> +//===-- NVPTXMCAsmInfo.cpp - NVPTX asm properties
>> -------------------------===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file contains the declarations of the NVPTXMCAsmInfo properties.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#include "NVPTXMCAsmInfo.h"
>> +#include "llvm/ADT/Triple.h"
>> +#include "llvm/Support/CommandLine.h"
>> +
>> +using namespace llvm;
>> +
>> +bool CompileForDebugging;
>> +
>> +// -debug-compile - Command line option to inform opt and llc passes to
>> +// compile for debugging
>> +static cl::opt<bool, true>
>> +Debug("debug-compile", cl::desc("Compile for debugging"), cl::Hidden,
>> + cl::location(CompileForDebugging),
>> + cl::init(false));
>> +
>> +void NVPTXMCAsmInfo::anchor() { }
>> +
>> +NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Target &T, const StringRef &TT) {
>> + Triple TheTriple(TT);
>> + if (TheTriple.getArch() == Triple::nvptx64)
>> + PointerSize = 8;
>> +
>> + CommentString = "//";
>> +
>> + PrivateGlobalPrefix = "$L__";
>> +
>> + AllowPeriodsInName = false;
>> +
>> + HasSetDirective = false;
>> +
>> + HasSingleParameterDotFile = false;
>> +
>> + InlineAsmStart = " inline asm";
>> + InlineAsmEnd = " inline asm";
>> +
>> + SupportsDebugInformation = CompileForDebugging;
>> + HasDotTypeDotSizeDirective = false;
>> +
>> + Data8bitsDirective = " .b8 ";
>> + Data16bitsDirective = " .b16 ";
>> + Data32bitsDirective = " .b32 ";
>> + Data64bitsDirective = " .b64 ";
>> + PrivateGlobalPrefix = "";
>> + ZeroDirective = " .b8";
>> + AsciiDirective = " .b8";
>> + AscizDirective = " .b8";
>> +
>> + // @TODO: Can we just disable this?
>> + GlobalDirective = "\t// .globl\t";
>> +}
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,30 @@
>> +//===-- NVPTXMCAsmInfo.h - NVPTX asm properties ----------------*- C++
>> -*--===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file contains the declaration of the NVPTXMCAsmInfo class.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#ifndef NVPTX_MCASM_INFO_H
>> +#define NVPTX_MCASM_INFO_H
>> +
>> +#include "llvm/MC/MCAsmInfo.h"
>> +
>> +namespace llvm {
>> +class Target;
>> +class StringRef;
>> +
>> +class NVPTXMCAsmInfo : public MCAsmInfo {
>> + virtual void anchor();
>> +public:
>> + explicit NVPTXMCAsmInfo(const Target &T, const StringRef &TT);
>> +};
>> +} // namespace llvm
>> +
>> +#endif // NVPTX_MCASM_INFO_H
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp Fri
>> May 4 15:18:50 2012
>> @@ -0,0 +1,91 @@
>> +//===-- NVPTXMCTargetDesc.cpp - NVPTX Target Descriptions -------*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file provides NVPTX specific target descriptions.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#include "NVPTXMCTargetDesc.h"
>> +#include "NVPTXMCAsmInfo.h"
>> +#include "llvm/MC/MCCodeGenInfo.h"
>> +#include "llvm/MC/MCInstrInfo.h"
>> +#include "llvm/MC/MCRegisterInfo.h"
>> +#include "llvm/MC/MCSubtargetInfo.h"
>> +#include "llvm/Support/TargetRegistry.h"
>> +
>> +#define GET_INSTRINFO_MC_DESC
>> +#include "NVPTXGenInstrInfo.inc"
>> +
>> +#define GET_SUBTARGETINFO_MC_DESC
>> +#include "NVPTXGenSubtargetInfo.inc"
>> +
>> +#define GET_REGINFO_MC_DESC
>> +#include "NVPTXGenRegisterInfo.inc"
>> +
>> +
>> +using namespace llvm;
>> +
>> +static MCInstrInfo *createNVPTXMCInstrInfo() {
>> + MCInstrInfo *X = new MCInstrInfo();
>> + InitNVPTXMCInstrInfo(X);
>> + return X;
>> +}
>> +
>> +static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {
>> + MCRegisterInfo *X = new MCRegisterInfo();
>> + // PTX does not have a return address register.
>> + InitNVPTXMCRegisterInfo(X, 0);
>> + return X;
>> +}
>> +
>> +static MCSubtargetInfo *createNVPTXMCSubtargetInfo(StringRef TT,
>> StringRef CPU,
>> + StringRef FS) {
>> + MCSubtargetInfo *X = new MCSubtargetInfo();
>> + InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
>> + return X;
>> +}
>> +
>> +static MCCodeGenInfo *createNVPTXMCCodeGenInfo(StringRef TT,
>> Reloc::Model RM,
>> + CodeModel::Model CM,
>> + CodeGenOpt::Level OL) {
>> + MCCodeGenInfo *X = new MCCodeGenInfo();
>> + X->InitMCCodeGenInfo(RM, CM, OL);
>> + return X;
>> +}
>> +
>> +
>> +// Force static initialization.
>> +extern "C" void LLVMInitializeNVPTXTargetMC() {
>> + // Register the MC asm info.
>> + RegisterMCAsmInfo<NVPTXMCAsmInfo> X(TheNVPTXTarget32);
>> + RegisterMCAsmInfo<NVPTXMCAsmInfo> Y(TheNVPTXTarget64);
>> +
>> + // Register the MC codegen info.
>> + TargetRegistry::RegisterMCCodeGenInfo(TheNVPTXTarget32,
>> + createNVPTXMCCodeGenInfo);
>> + TargetRegistry::RegisterMCCodeGenInfo(TheNVPTXTarget64,
>> + createNVPTXMCCodeGenInfo);
>> +
>> + // Register the MC instruction info.
>> + TargetRegistry::RegisterMCInstrInfo(TheNVPTXTarget32,
>> createNVPTXMCInstrInfo);
>> + TargetRegistry::RegisterMCInstrInfo(TheNVPTXTarget64,
>> createNVPTXMCInstrInfo);
>> +
>> + // Register the MC register info.
>> + TargetRegistry::RegisterMCRegInfo(TheNVPTXTarget32,
>> + createNVPTXMCRegisterInfo);
>> + TargetRegistry::RegisterMCRegInfo(TheNVPTXTarget64,
>> + createNVPTXMCRegisterInfo);
>> +
>> + // Register the MC subtarget info.
>> + TargetRegistry::RegisterMCSubtargetInfo(TheNVPTXTarget32,
>> + createNVPTXMCSubtargetInfo);
>> + TargetRegistry::RegisterMCSubtargetInfo(TheNVPTXTarget64,
>> + createNVPTXMCSubtargetInfo);
>> +
>> +}
>>
>> Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h Fri May
>> 4 15:18:50 2012
>> @@ -0,0 +1,36 @@
>> +//===-- NVPTXMCTargetDesc.h - NVPTX Target Descriptions ---------*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file provides NVPTX specific target descriptions.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#ifndef NVPTXMCTARGETDESC_H
>> +#define NVPTXMCTARGETDESC_H
>> +
>> +namespace llvm {
>> +class Target;
>> +
>> +extern Target TheNVPTXTarget32;
>> +extern Target TheNVPTXTarget64;
>> +
>> +} // End llvm namespace
>> +
>> +// Defines symbolic names for PTX registers.
>> +#define GET_REGINFO_ENUM
>> +#include "NVPTXGenRegisterInfo.inc"
>> +
>> +// Defines symbolic names for the PTX instructions.
>> +#define GET_INSTRINFO_ENUM
>> +#include "NVPTXGenInstrInfo.inc"
>> +
>> +#define GET_SUBTARGETINFO_ENUM
>> +#include "NVPTXGenSubtargetInfo.inc"
>> +
>> +#endif
>>
>> Added: llvm/trunk/lib/Target/NVPTX/Makefile
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/Makefile?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/Makefile (added)
>> +++ llvm/trunk/lib/Target/NVPTX/Makefile Fri May 4 15:18:50 2012
>> @@ -0,0 +1,23 @@
>> +##===- lib/Target/NVPTX/Makefile ---------------------------*- Makefile
>> -*-===##
>> +#
>> +# The LLVM Compiler Infrastructure
>> +#
>> +# This file is distributed under the University of Illinois Open Source
>> +# License. See LICENSE.TXT for details.
>> +#
>>
>> +##===----------------------------------------------------------------------===##
>> +
>> +LEVEL = ../../..
>> +LIBRARYNAME = LLVMNVPTXCodeGen
>> +TARGET = NVPTX
>> +
>> +# Make sure that tblgen is run, first thing.
>> +BUILT_SOURCES = NVPTXGenAsmWriter.inc \
>> + NVPTXGenDAGISel.inc \
>> + NVPTXGenInstrInfo.inc \
>> + NVPTXGenRegisterInfo.inc \
>> + NVPTXGenSubtargetInfo.inc
>> +
>> +DIRS = InstPrinter TargetInfo MCTargetDesc
>> +
>> +include $(LEVEL)/Makefile.common
>>
>> Added: llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h Fri May 4 15:18:50
>> 2012
>> @@ -0,0 +1,49 @@
>> +//===-- ManagedStringPool.h - Managed String Pool ---------------*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// The strings allocated from a managed string pool are owned by the
>> string
>> +// pool and will be deleted together with the managed string pool.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +
>> +#ifndef LLVM_SUPPORT_MANAGED_STRING_H
>> +#define LLVM_SUPPORT_MANAGED_STRING_H
>> +
>> +#include "llvm/ADT/SmallVector.h"
>> +#include <string>
>> +
>> +namespace llvm {
>> +
>> +/// ManagedStringPool - The strings allocated from a managed string pool
>> are
>> +/// owned by the string pool and will be deleted together with the
>> managed
>> +/// string pool.
>> +class ManagedStringPool {
>> + SmallVector<std::string *, 8> Pool;
>> +
>> +public:
>> + ManagedStringPool() {}
>> + ~ManagedStringPool() {
>> + SmallVector<std::string *, 8>::iterator Current = Pool.begin();
>> + while (Current != Pool.end()) {
>> + delete *Current;
>> + Current++;
>> + }
>> + }
>> +
>> + std::string *getManagedString(const char *S) {
>> + std::string *Str = new std::string(S);
>> + Pool.push_back(Str);
>> + return Str;
>> + }
>> +};
>> +
>> +}
>> +
>> +#endif
>>
>> Added: llvm/trunk/lib/Target/NVPTX/NVPTX.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTX.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTX.h Fri May 4 15:18:50 2012
>> @@ -0,0 +1,137 @@
>> +//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file contains the entry points for global functions defined in
>> +// the LLVM NVPTX back-end.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#ifndef LLVM_TARGET_NVPTX_H
>> +#define LLVM_TARGET_NVPTX_H
>> +
>> +#include <cassert>
>> +#include <iosfwd>
>> +#include "llvm/Value.h"
>> +#include "llvm/Module.h"
>> +#include "llvm/Support/ErrorHandling.h"
>> +#include "llvm/Target/TargetMachine.h"
>> +#include "MCTargetDesc/NVPTXBaseInfo.h"
>> +
>> +namespace llvm {
>> +class NVPTXTargetMachine;
>> +class FunctionPass;
>> +class formatted_raw_ostream;
>> +
>> +namespace NVPTXCC {
>> +enum CondCodes {
>> + EQ,
>> + NE,
>> + LT,
>> + LE,
>> + GT,
>> + GE
>> +};
>> +}
>> +
>> +inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
>> + switch (CC) {
>> + default: assert(0 && "Unknown condition code");
>> + case NVPTXCC::NE: return "ne";
>> + case NVPTXCC::EQ: return "eq";
>> + case NVPTXCC::LT: return "lt";
>> + case NVPTXCC::LE: return "le";
>> + case NVPTXCC::GT: return "gt";
>> + case NVPTXCC::GE: return "ge";
>> + }
>> +}
>> +
>> +FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
>> + llvm::CodeGenOpt::Level OptLevel);
>> +FunctionPass *createVectorElementizePass(NVPTXTargetMachine &);
>> +FunctionPass *createLowerStructArgsPass(NVPTXTargetMachine &);
>> +FunctionPass *createNVPTXReMatPass(NVPTXTargetMachine &);
>> +FunctionPass *createNVPTXReMatBlockPass(NVPTXTargetMachine &);
>> +
>> +bool isImageOrSamplerVal(const Value *, const Module *);
>> +
>> +extern Target TheNVPTXTarget32;
>> +extern Target TheNVPTXTarget64;
>> +
>> +namespace NVPTX
>> +{
>> +enum DrvInterface {
>> + NVCL,
>> + CUDA,
>> + TEST
>> +};
>> +
>> +// A field inside TSFlags needs a shift and a mask. The usage is
>> +// always as follows :
>> +// ((TSFlags & fieldMask) >> fieldShift)
>> +// The enum keeps the mask, the shift, and all valid values of the
>> +// field in one place.
>> +enum VecInstType {
>> + VecInstTypeShift = 0,
>> + VecInstTypeMask = 0xF,
>> +
>> + VecNOP = 0,
>> + VecLoad = 1,
>> + VecStore = 2,
>> + VecBuild = 3,
>> + VecShuffle = 4,
>> + VecExtract = 5,
>> + VecInsert = 6,
>> + VecDest = 7,
>> + VecOther = 15
>> +};
>> +
>> +enum SimpleMove {
>> + SimpleMoveMask = 0x10,
>> + SimpleMoveShift = 4
>> +};
>> +enum LoadStore {
>> + isLoadMask = 0x20,
>> + isLoadShift = 5,
>> + isStoreMask = 0x40,
>> + isStoreShift = 6
>> +};
>> +
>> +namespace PTXLdStInstCode {
>> +enum AddressSpace{
>> + GENERIC = 0,
>> + GLOBAL = 1,
>> + CONSTANT = 2,
>> + SHARED = 3,
>> + PARAM = 4,
>> + LOCAL = 5
>> +};
>> +enum FromType {
>> + Unsigned = 0,
>> + Signed,
>> + Float
>> +};
>> +enum VecType {
>> + Scalar = 1,
>> + V2 = 2,
>> + V4 = 4
>> +};
>> +}
>> +}
>> +} // end namespace llvm;
>> +
>> +// Defines symbolic names for NVPTX registers. This defines a mapping
>> from
>> +// register name to register number.
>> +#define GET_REGINFO_ENUM
>> +#include "NVPTXGenRegisterInfo.inc"
>> +
>> +// Defines symbolic names for the NVPTX instructions.
>> +#define GET_INSTRINFO_ENUM
>> +#include "NVPTXGenInstrInfo.inc"
>> +
>> +#endif
>>
>> Added: llvm/trunk/lib/Target/NVPTX/NVPTX.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.td?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTX.td (added)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTX.td Fri May 4 15:18:50 2012
>> @@ -0,0 +1,44 @@
>> +//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen
>> -*-==//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +// This is the top level entry point for the NVPTX target.
>>
>> +//===----------------------------------------------------------------------===//
>> +
>>
>> +//===----------------------------------------------------------------------===//
>> +// Target-independent interfaces
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +include "llvm/Target/Target.td"
>> +
>> +include "NVPTXRegisterInfo.td"
>> +include "NVPTXInstrInfo.td"
>> +
>>
>> +//===----------------------------------------------------------------------===//
>> +// Subtarget Features.
>> +// - We use the SM version number instead of explicit feature table.
>> +// - Need at least one feature to avoid generating zero sized array by
>> +// TableGen in NVPTXGenSubtarget.inc.
>>
>> +//===----------------------------------------------------------------------===//
>> +def FeatureDummy : SubtargetFeature<"dummy", "dummy", "true", "">;
>> +
>>
>> +//===----------------------------------------------------------------------===//
>> +// NVPTX supported processors.
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +class Proc<string Name, list<SubtargetFeature> Features>
>> + : Processor<Name, NoItineraries, Features>;
>> +
>> +def : Proc<"sm_10", [FeatureDummy]>;
>> +
>> +
>> +def NVPTXInstrInfo : InstrInfo {
>> +}
>> +
>> +def NVPTX : Target {
>> + let InstructionSet = NVPTXInstrInfo;
>> +}
>>
>> Added: llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp (added)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp Fri May 4
>> 15:18:50 2012
>> @@ -0,0 +1,48 @@
>> +//===-- AllocaHoisting.cpp - Hosist allocas to the entry block --*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// Hoist the alloca instructions in the non-entry blocks to the entry
>> blocks.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#include "llvm/Function.h"
>> +#include "llvm/Instructions.h"
>> +#include "llvm/Constants.h"
>> +#include "NVPTXAllocaHoisting.h"
>> +
>> +namespace llvm {
>> +
>> +bool NVPTXAllocaHoisting::runOnFunction(Function &function) {
>> + bool functionModified = false;
>> + Function::iterator I = function.begin();
>> + TerminatorInst *firstTerminatorInst = (I++)->getTerminator();
>> +
>> + for (Function::iterator E = function.end(); I != E; ++I) {
>> + for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;)
>> {
>> + AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);
>> + if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {
>> + allocaInst->moveBefore(firstTerminatorInst);
>> + functionModified = true;
>> + }
>> + }
>> + }
>> +
>> + return functionModified;
>> +}
>> +
>> +char NVPTXAllocaHoisting::ID = 1;
>> +RegisterPass<NVPTXAllocaHoisting> X("alloca-hoisting",
>> + "Hoisting alloca instructsion in
>> non-entry "
>> + "blocks to the entry block");
>> +
>> +FunctionPass *createAllocaHoisting() {
>> + return new NVPTXAllocaHoisting();
>> +}
>> +
>> +} // end namespace llvm
>>
>> Added: llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h (added)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h Fri May 4 15:18:50
>> 2012
>> @@ -0,0 +1,49 @@
>> +//===-- AllocaHoisting.h - Hosist allocas to the entry block ----*- C++
>> -*-===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// Hoist the alloca instructions in the non-entry blocks to the entry
>> blocks.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#ifndef NVPTX_ALLOCA_HOISTING_H_
>> +#define NVPTX_ALLOCA_HOISTING_H_
>> +
>> +#include "llvm/CodeGen/MachineFunctionAnalysis.h"
>> +#include "llvm/Pass.h"
>> +#include "llvm/Target/TargetData.h"
>> +
>> +namespace llvm {
>> +
>> +class FunctionPass;
>> +class Function;
>> +
>> +// Hoisting the alloca instructions in the non-entry blocks to the entry
>> +// block.
>> +class NVPTXAllocaHoisting : public FunctionPass {
>> +public:
>> + static char ID; // Pass ID
>> + NVPTXAllocaHoisting() : FunctionPass(ID) {}
>> +
>> + void getAnalysisUsage(AnalysisUsage &AU) const {
>> + AU.addRequired<TargetData>();
>> + AU.addPreserved<MachineFunctionAnalysis>();
>> + }
>> +
>> + virtual const char *getPassName() const {
>> + return "NVPTX specific alloca hoisting";
>> + }
>> +
>> + virtual bool runOnFunction(Function &function);
>> +};
>> +
>> +extern FunctionPass *createAllocaHoisting();
>> +
>> +} // end namespace llvm
>> +
>> +#endif // NVPTX_ALLOCA_HOISTING_H_
>>
>> Added: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=156196&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (added)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp Fri May 4 15:18:50
>> 2012
>> @@ -0,0 +1,2068 @@
>> +//===-- NVPTXAsmPrinter.cpp - NVPTX LLVM assembly writer
>> ------------------===//
>> +//
>> +// The LLVM Compiler Infrastructure
>> +//
>> +// This file is distributed under the University of Illinois Open Source
>> +// License. See LICENSE.TXT for details.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +//
>> +// This file contains a printer that converts from our internal
>> representation
>> +// of machine-dependent LLVM code to NVPTX assembly language.
>> +//
>>
>> +//===----------------------------------------------------------------------===//
>> +
>> +#include "NVPTX.h"
>> +#include "NVPTXInstrInfo.h"
>> +#include "NVPTXTargetMachine.h"
>> +#include "NVPTXRegisterInfo.h"
>> +#include "NVPTXAsmPrinter.h"
>> +#include "MCTargetDesc/NVPTXMCAsmInfo.h"
>> +#include "NVPTXNumRegisters.h"
>> +#include "../lib/CodeGen/AsmPrinter/DwarfDebug.h"
>> +#include "llvm/ADT/StringExtras.h"
>> +#include "llvm/GlobalVariable.h"
>> +#include "llvm/Function.h"
>> +#include "llvm/Module.h"
>> +#include "llvm/CodeGen/Analysis.h"
>> +#include "llvm/CodeGen/MachineRegisterInfo.h"
>> +#include "llvm/CodeGen/MachineFrameInfo.h"
>> +#include "llvm/CodeGen/MachineModuleInfo.h"
>> +#include "llvm/MC/MCStreamer.h"
>> +#include "llvm/MC/MCSymbol.h"
>> +#include "llvm/Target/Mangler.h"
>> +#include "llvm/Target/TargetLoweringObjectFile.h"
>> +#include "llvm/Support/TargetRegistry.h"
>> +#include "llvm/Support/ErrorHandling.h"
>> +#include "llvm/Support/FormattedStream.h"
>> +#include "llvm/DerivedTypes.h"
>> +#include "NVPTXUtilities.h"
>> +#include "llvm/Support/TimeValue.h"
>> +#include <sstream>
>> +#include "llvm/Support/CommandLine.h"
>> +#include "llvm/Analysis/DebugInfo.h"
>> +#include "llvm/Analysis/ConstantFolding.h"
>> +#include "llvm/Support/Path.h"
>> +#include "llvm/Assembly/Writer.h"
>> +#include "cl_common_defines.h"
>> +
>> +
>> +using namespace llvm;
>> +
>> +
>> +#include "NVPTXGenAsmWriter.inc"
>> +
>> +bool RegAllocNilUsed = true;
>> +
>> +#define DEPOTNAME "__local_depot"
>> +
>> +static cl::opt<bool>
>> +EmitLineNumbers("nvptx-emit-line-numbers",
>> + cl::desc("NVPTX Specific: Emit Line numbers even without
>> -G"),
>> + cl::init(true));
>> +
>> +namespace llvm {
>> +bool InterleaveSrcInPtx = false;
>> +}
>> +
>> +static cl::opt<bool, true>InterleaveSrc("nvptx-emit-src",
>> + cl::ZeroOrMore,
>> + cl::desc("NVPTX Specific: Emit source line in ptx
>> file"),
>> +
>> cl::location(llvm::InterleaveSrcInPtx));
>> +
>> +
>> +
>> +
>> +// @TODO: This is a copy from AsmPrinter.cpp. The function is static,
>> so we
>> +// cannot just link to the existing version.
>> +/// LowerConstant - Lower the specified LLVM Constant to an MCExpr.
>> +///
>> +using namespace nvptx;
>> +const MCExpr *nvptx::LowerConstant(const Constant *CV, AsmPrinter &AP) {
>> + MCContext &Ctx = AP.OutContext;
>> +
>> + if (CV->isNullValue() || isa<UndefValue>(CV))
>> + return MCConstantExpr::Create(0, Ctx);
>> +
>> + if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV))
>> + return MCConstantExpr::Create(CI->getZExtValue(), Ctx);
>> +
>> + if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV))
>> + return MCSymbolRefExpr::Create(AP.Mang->getSymbol(GV), Ctx);
>> +
>> + if (const BlockAddress *BA = dyn_cast<BlockAddress>(CV))
>> + return MCSymbolRefExpr::Create(AP.GetBlockAddressSymbol(BA), Ctx);
>> +
>> + const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV);
>> + if (CE == 0)
>> + llvm_unreachable("Unknown constant value to lower!");
>> +
>> +
>> + switch (CE->getOpcode()) {
>> + default:
>> + // If the code isn't optimized, there may be outstanding folding
>> + // opportunities. Attempt to fold the expression using TargetData as
>> a
>> + // last resort before giving up.
>> + if (Constant *C =
>> + ConstantFoldConstantExpression(CE, AP.TM.getTargetData()))
>> + if (C != CE)
>> + return LowerConstant(C, AP);
>> +
>> + // Otherwise report the problem to the user.
>> + {
>> + std::string S;
>> + raw_string_ostream OS(S);
>> + OS << "Unsupported expression in static initializer: ";
>> + WriteAsOperand(OS, CE, /*PrintType=*/false,
>> + !AP.MF ? 0 : AP.MF->getFunction()->getParent());
>> + report_fatal_error(OS.str());
>> + }
>> + case Instruction::GetElementPtr: {
>> + const TargetData &TD = *AP.TM.getTargetData();
>> + // Generate a symbolic expression for the byte address
>> + const Constant *PtrVal = CE->getOperand(0);
>> + SmallVector<Value*, 8> IdxVec(CE->op_begin()+1, CE->op_end());
>> + int64_t Offset = TD.getIndexedOffset(PtrVal->getType(), IdxVec);
>> +
>> + const MCExpr *Base = LowerConstant(CE->getOperand(0), AP);
>> + if (Offset == 0)
>> + return Base;
>> +
>> + // Truncate/sext the offset to the pointer size.
>> + if (TD.getPointerSizeInBits() != 64) {
>> + int SExtAmount = 64-TD.getPointerSizeInBits();
>> + Offset = (Offset << SExtAmount) >> SExtAmount;
>> + }
>> +
>> + return MCBinaryExpr::CreateAdd(Base, MCConstantExpr::Create(Offset,
>> Ctx),
>> + Ctx);
>> + }
>> +
>> + case Instruction::Trunc:
>> + // We emit the value and depend on the assembler to truncate the
>> generated
>> + // expression properly. This is important for differences between
>> + // blockaddress labels. Since the two labels are in the same
>> function, it
>> + // is reasonable to treat their delta as a 32-bit value.
>> + // FALL THROUGH.
>> + case Instruction::BitCast:
>> + return LowerConstant(CE->getOperand(0), AP);
>> +
>> + case Instruction::IntToPtr: {
>> + const TargetData &TD = *AP.TM.getTargetData();
>> + // Handle casts to pointers by changing them into casts to the
>> appropriate
>> + // integer type. This promotes constant folding and simplifies this
>> code.
>> + Constant *Op = CE->getOperand(0);
>> + Op = ConstantExpr::getIntegerCast(Op,
>> TD.getIntPtrType(CV->getContext()),
>> + false/*ZExt*/);
>> + return LowerConstant(Op, AP);
>> + }
>> +
>> + case Instruction::PtrToInt: {
>> + const TargetData &TD = *AP.TM.getTargetData();
>> + // Support only foldable casts to/from pointers that can be
>> eliminated by
>> + // changing the pointer to the appropriately sized integer type.
>> + Constant *Op = CE->getOperand(0);
>> + Type *Ty = CE->getType();
>> +
>> + const MCExpr *OpExpr = LowerConstant(Op, AP);
>> +
>> + // We can emit the pointer value into this slot if the slot is an
>> + // integer slot equal to the size of the pointer.
>> + if (TD.getTypeAllocSize(Ty) == TD.getTypeAllocSize(Op->getType()))
>> + return OpExpr;
>> +
>> + // Otherwise the pointer is smaller than the resultant integer, mask
>> off
>> + // the high bits so we are sure to get a proper truncation if the
>> input is
>> + // a constant expr.
>> + unsigned InBits = TD.getTypeAllocSizeInBits(Op->getType());
>> + const MCExpr *MaskExpr = MCConstantExpr::Create(~0ULL >>
>> (64-InBits), Ctx);
>> + return MCBinaryExpr::CreateAnd(OpExpr, MaskExpr, Ctx);
>> + }
>> +
>> + // The MC library also has a right-shift operator, but it isn't
>> consistently
>> + // signed or unsigned between different targets.
>> + case Instruction::Add:
>> + case Instruction::Sub:
>> + case Instruction::Mul:
>> + case Instruction::SDiv:
>> + case Instruction::SRem:
>> + case Instruction::Shl:
>> + case Instruction::And:
>> + case Instruction::Or:
>> + case Instruction::Xor: {
>> + const MCExpr *LHS = LowerConstant(CE->getOperand(0), AP);
>> + const MCExpr *RHS = LowerConstant(CE->getOperand(1), AP);
>> + switch (CE->getOpcode()) {
>> + default: llvm_unreachable("Unknown binary operator constant cast
>> expr");
>> + case Instruction::Add: return MCBinaryExpr::CreateAdd(LHS, RHS, Ctx);
>> + case Instruction::Sub: return MCBinaryExpr::CreateSub(LHS, RHS, Ctx);
>> + case Instruction::Mul: return MCBinaryExpr::CreateMul(LHS, RHS, Ctx);
>> + case Instruction::SDiv: return MCBinaryExpr::CreateDiv(LHS, RHS,
>> Ctx);
>> + case Instruction::SRem: return MCBinaryExpr::CreateMod(LHS, RHS,
>> Ctx);
>> + case Instruction::Shl: return MCBinaryExpr::CreateShl(LHS, RHS, Ctx);
>> + case Instruction::And: return MCBinaryExpr::CreateAnd(LHS, RHS, Ctx);
>> + case Instruction::Or: return MCBinaryExpr::CreateOr (LHS, RHS, Ctx);
>> + case Instruction::Xor: return MCBinaryExpr::CreateXor(LHS, RHS, Ctx);
>> + }
>> + }
>> + }
>> +}
>> +
>> +
>> +void NVPTXAsmPrinter::emitLineNumberAsDotLoc(const MachineInstr &MI)
>> +{
>> + if (!EmitLineNumbers)
>> + return;
>> + if (ignoreLoc(MI))
>> + return;
>> +
>> + DebugLoc curLoc = MI.getDebugLoc();
>> +
>> + if (prevDebugLoc.isUnknown() && curLoc.isUnknown())
>> + return;
>> +
>> + if (prevDebugLoc == curLoc)
>> + return;
>> +
>> + prevDebugLoc = curLoc;
>> +
>> + if (curLoc.isUnknown())
>> + return;
>> +
>> +
>> + const MachineFunction *MF = MI.getParent()->getParent();
>> + //const TargetMachine &TM = MF->getTarget();
>> +
>> + const LLVMContext &ctx = MF->getFunction()->getContext();
>> + DIScope Scope(curLoc.getSc...
>>
>> [Message clipped]
>
>
>
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>
>
--
Thanks,
Justin Holewinski
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