[llvm-commits] [PATCH 01/11] (patch) Mips Inline asm 16 bit register allowed for GPR constraints

[Eric Christopher]

On Apr 12, 2012, at 1:24 PM, Jack Carter <jcarter at mips.com> wrote:

> When using inline asm constraints representing
> non-floating point general registers we were now
> allowing for 16 bit elements (shorts). This needed
> to be added so wecould test some of the other constraints
> that represent 16 bit elements.
> 
> The test for this will appear in the Constraint_I patch in
> this patch series.
> 
>     short s_input = 7;
>     short s_result = 0;
>     short s_val = -3;
> 
> /*
>        I - A signed 16 bit constant
> */
>     __asm__ __volatile__(
>           "addi %0,%1,%2\n\t "
> 	     : "=r" (s_result)
> 	     : "r" (s_input), "I" (s_val));
> 
> Without this patch "=r"(s_result) would produce an erroneous error.
> ---
> lib/Target/Mips/MipsISelLowering.cpp       |    2 +-
> test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll |   31 ++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+), 1 deletions(-)
> create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
> <reg_16.patch>_______________________________________________
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OK.

-eric