[llvm-commits] [llvm] r155522 - in /llvm/trunk: lib/Target/Mips/MipsMachineFunction.cpp test/CodeGen/Mips/2010-07-20-Switch.ll test/CodeGen/Mips/cmov.ll

[Akira Hatanaka]

Author: ahatanak
Date: Tue Apr 24 20:24:52 2012
New Revision: 155522

URL: http://llvm.org/viewvc/llvm-project?rev=155522&view=rev
Log:
Do not use $gp as a dedicated global register if the target ABI is not O32. 

Modified:
    llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
    llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
    llvm/trunk/test/CodeGen/Mips/cmov.ll

Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp?rev=155522&r1=155521&r2=155522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp Tue Apr 24 20:24:52 2012
@@ -37,8 +37,8 @@
 
   const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
 
-  if (FixGlobalBaseReg) // $gp is the global base register.
-    return GlobalBaseReg = ST.isABI_N64() ? Mips::GP_64 : Mips::GP;
+  if (FixGlobalBaseReg && ST.isABI_O32()) // $gp is the global base register.
+    return GlobalBaseReg = Mips::GP;
 
   const TargetRegisterClass *RC = ST.isABI_N64() ?
     (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :

Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=155522&r1=155521&r2=155522&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Tue Apr 24 20:24:52 2012
@@ -15,10 +15,11 @@
 ; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
 ; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp
 ; PIC-O32: jr  $[[R1]]
+; PIC-N64: daddiu $[[R2:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(main)))
 ; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
 ; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0)
 ; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3
-; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp
+; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $[[R2]]
 ; PIC-N64: jr  $[[R1]]
   switch i32 %0, label %bb4 [
     i32 0, label %bb5

Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=155522&r1=155521&r2=155522&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Tue Apr 24 20:24:52 2012
@@ -7,8 +7,8 @@
 
 ; O32:  lw  ${{[0-9]+}}, %got(i3)($gp)
 ; O32:  addiu ${{[0-9]+}}, $gp, %got(i1)
-; N64:  ld  ${{[0-9]+}}, %got_disp(i3)($gp)
-; N64:  daddiu ${{[0-9]+}}, $gp, %got_disp(i1)
+; N64:  ld  ${{[0-9]+}}, %got_disp(i3)
+; N64:  daddiu ${{[0-9]+}}, ${{[0-9]+}}, %got_disp(i1)
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
@@ -25,8 +25,8 @@
 ; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
 ; O32: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
 ; N64: cmov2:
-; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d)
-; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c)
+; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
+; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; N64: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
 define i32 @cmov2(i32 %s) nounwind readonly {
 entry: