[llvm-commits] [llvm] r155486 - in /llvm/trunk: include/llvm/CodeGen/MachineScheduler.h lib/CodeGen/MachineScheduler.cpp

[Andrew Trick]

Author: atrick
Date: Tue Apr 24 15:36:19 2012
New Revision: 155486

URL: http://llvm.org/viewvc/llvm-project?rev=155486&view=rev
Log:
Fix a naughty header include that breaks "installed" builds.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
    llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=155486&r1=155485&r2=155486&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Tue Apr 24 15:36:19 2012
@@ -27,7 +27,6 @@
 #ifndef MACHINESCHEDULER_H
 #define MACHINESCHEDULER_H
 
-#include "RegisterClassInfo.h"
 #include "llvm/CodeGen/MachinePassRegistry.h"
 
 namespace llvm {
@@ -36,6 +35,7 @@
 class LiveIntervals;
 class MachineDominatorTree;
 class MachineLoopInfo;
+class RegClassInfo;
 class ScheduleDAGInstrs;
 
 /// MachineSchedContext provides enough context from the MachineScheduler pass
@@ -48,10 +48,10 @@
   AliasAnalysis *AA;
   LiveIntervals *LIS;
 
-  RegisterClassInfo RegClassInfo;
+  RegisterClassInfo *RegClassInfo;
 
-  MachineSchedContext():
-    MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
+  MachineSchedContext();
+  virtual ~MachineSchedContext();
 };
 
 /// MachineSchedRegistry provides a selection of available machine instruction

Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=155486&r1=155485&r2=155486&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Apr 24 15:36:19 2012
@@ -14,6 +14,7 @@
 
 #define DEBUG_TYPE "misched"
 
+#include "RegisterClassInfo.h"
 #include "RegisterPressure.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/MachineScheduler.h"
@@ -51,6 +52,15 @@
 // Machine Instruction Scheduling Pass and Registry
 //===----------------------------------------------------------------------===//
 
+MachineSchedContext::MachineSchedContext():
+    MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
+  RegClassInfo = new RegisterClassInfo();
+}
+
+MachineSchedContext::~MachineSchedContext() {
+  delete RegClassInfo;
+}
+
 namespace {
 /// MachineScheduler runs after coalescing and before register allocation.
 class MachineScheduler : public MachineSchedContext,
@@ -173,7 +183,7 @@
   LIS = &getAnalysis<LiveIntervals>();
   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 
-  RegClassInfo.runOnMachineFunction(*MF);
+  RegClassInfo->runOnMachineFunction(*MF);
 
   // Select the scheduler, or set the default.
   MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
@@ -328,7 +338,7 @@
 public:
   ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
     ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
-    AA(C->AA), RegClassInfo(&C->RegClassInfo), SchedImpl(S),
+    AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
     RPTracker(RegPressure), CurrentTop(), CurrentBottom(),
     NumInstrsScheduled(0) {}