[llvm-commits] [llvm] r155456 - in /llvm/trunk: include/llvm/CodeGen/MachineScheduler.h include/llvm/CodeGen/ScheduleDAGInstrs.h lib/CodeGen/MachineScheduler.cpp lib/CodeGen/ScheduleDAGInstrs.cpp
Chandler Carruth
chandlerc at google.com
Tue Apr 24 12:03:43 PDT 2012
On Tue, Apr 24, 2012 at 10:56 AM, Andrew Trick <atrick at apple.com> wrote:
> Author: atrick
> Date: Tue Apr 24 12:56:43 2012
> New Revision: 155456
>
> URL: http://llvm.org/viewvc/llvm-project?rev=155456&view=rev
> Log:
> misched: DAG builder support for tracking register pressure within the
> current scheduling region.
>
> The DAG builder is a convenient place to do it. Hopefully this is more
> efficient than a separate traversal over the same region.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
> llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
> llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=155456&r1=155455&r2=155456&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Tue Apr 24 12:56:43
> 2012
> @@ -27,6 +27,7 @@
> #ifndef MACHINESCHEDULER_H
> #define MACHINESCHEDULER_H
>
> +#include "RegisterClassInfo.h"
>
This doesn't seem right Andy... we're including a header from lib/CodeGen
into a file in include/llvm/CodeGen. The latter files get installed, the
former don't... It's breaking installed library usage (and it's breaking
our layering checked builds).
Thoughts? Should this include go away? Should RegisterClassInfo.h move?
> #include "llvm/CodeGen/MachinePassRegistry.h"
>
> namespace llvm {
> @@ -47,7 +48,10 @@
> AliasAnalysis *AA;
> LiveIntervals *LIS;
>
> - MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0),
> LIS(0) {}
> + RegisterClassInfo RegClassInfo;
> +
> + MachineSchedContext():
> + MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
> };
>
> /// MachineSchedRegistry provides a selection of available machine
> instruction
>
> Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h?rev=155456&r1=155455&r2=155456&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h Tue Apr 24
> 12:56:43 2012
> @@ -28,6 +28,7 @@
> class MachineLoopInfo;
> class MachineDominatorTree;
> class LiveIntervals;
> + class RegPressureTracker;
>
> /// LoopDependencies - This class analyzes loop-oriented register
> /// dependencies, which are used to guide scheduling decisions.
> @@ -275,7 +276,7 @@
>
> /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we
> are
> /// input.
> - void buildSchedGraph(AliasAnalysis *AA);
> + void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker
> = 0);
>
> /// addSchedBarrierDeps - Add dependencies from instructions in the
> current
> /// list of instructions being scheduled to scheduling barrier. We
> want to
>
> Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=155456&r1=155455&r2=155456&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Apr 24 12:56:43 2012
> @@ -14,6 +14,7 @@
>
> #define DEBUG_TYPE "misched"
>
> +#include "RegisterPressure.h"
> #include "llvm/CodeGen/LiveIntervalAnalysis.h"
> #include "llvm/CodeGen/MachineScheduler.h"
> #include "llvm/CodeGen/Passes.h"
> @@ -149,6 +150,8 @@
> LIS = &getAnalysis<LiveIntervals>();
> const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
>
> + RegClassInfo.runOnMachineFunction(*MF);
> +
> // Select the scheduler, or set the default.
> MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
> if (Ctor == useDefaultMachineSched) {
> @@ -163,6 +166,9 @@
> OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
>
> // Visit all machine basic blocks.
> + //
> + // TODO: Visit blocks in global postorder or postorder within the
> bottom-up
> + // loop tree. Then we can optionally compute global RegPressure.
> for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
> MBB != MBBEnd; ++MBB) {
>
> @@ -181,6 +187,7 @@
> unsigned RemainingCount = MBB->size();
> for(MachineBasicBlock::iterator RegionEnd = MBB->end();
> RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
> +
> // Avoid decrementing RegionEnd for blocks with no terminator.
> if (RegionEnd != MBB->end()
> || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
> @@ -279,8 +286,13 @@
> /// machine instructions while updating LiveIntervals.
> class ScheduleDAGMI : public ScheduleDAGInstrs {
> AliasAnalysis *AA;
> + RegisterClassInfo *RegClassInfo;
> MachineSchedStrategy *SchedImpl;
>
> + // Register pressure in this region computed by buildSchedGraph.
> + IntervalPressure RegPressure;
> + RegPressureTracker RPTracker;
> +
> /// The top of the unscheduled zone.
> MachineBasicBlock::iterator CurrentTop;
>
> @@ -293,7 +305,8 @@
> public:
> ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
> ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false,
> C->LIS),
> - AA(C->AA), SchedImpl(S), CurrentTop(), CurrentBottom(),
> + AA(C->AA), RegClassInfo(&C->RegClassInfo), SchedImpl(S),
> + RPTracker(RegPressure), CurrentTop(), CurrentBottom(),
> NumInstrsScheduled(0) {}
>
> ~ScheduleDAGMI() {
> @@ -303,7 +316,16 @@
> MachineBasicBlock::iterator top() const { return CurrentTop; }
> MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
>
> - /// Implement ScheduleDAGInstrs interface.
> + /// Implement the ScheduleDAGInstrs interface for handling the next
> scheduling
> + /// region. This covers all instructions in a block, while schedule()
> may only
> + /// cover a subset.
> + void enterRegion(MachineBasicBlock *bb,
> + MachineBasicBlock::iterator begin,
> + MachineBasicBlock::iterator end,
> + unsigned endcount);
> +
> + /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
> + /// reorderable instructions.
> void schedule();
>
> protected:
> @@ -392,10 +414,32 @@
> return true;
> }
>
> +/// enterRegion - Called back from MachineScheduler::runOnMachineFunction
> after
> +/// crossing a scheduling boundary. [begin, end) includes all
> instructions in
> +/// the region, including the boundary itself and single-instruction
> regions
> +/// that don't get scheduled.
> +void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
> + MachineBasicBlock::iterator begin,
> + MachineBasicBlock::iterator end,
> + unsigned endcount)
> +{
> + ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);
> + // Setup the register pressure tracker to begin tracking at the end of
> this
> + // region.
> + RPTracker.init(&MF, RegClassInfo, LIS, BB, end);
> +}
> +
> /// schedule - Called back from MachineScheduler::runOnMachineFunction
> -/// after setting up the current scheduling region.
> +/// after setting up the current scheduling region. [RegionBegin,
> RegionEnd)
> +/// only includes instructions that have DAG nodes, not scheduling
> boundaries.
> void ScheduleDAGMI::schedule() {
> - buildSchedGraph(AA);
> + while(RPTracker.getPos() != RegionEnd) {
> + bool Moved = RPTracker.recede();
> + assert(Moved && "Regpressure tracker cannot find RegionEnd");
> (void)Moved;
> + }
> +
> + // Build the DAG.
> + buildSchedGraph(AA, &RPTracker);
>
> DEBUG(dbgs() << "********** MI Scheduling **********\n");
> DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
>
> Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=155456&r1=155455&r2=155456&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Apr 24 12:56:43 2012
> @@ -13,6 +13,7 @@
>
> //===----------------------------------------------------------------------===//
>
> #define DEBUG_TYPE "sched-instrs"
> +#include "RegisterPressure.h"
> #include "llvm/Operator.h"
> #include "llvm/Analysis/AliasAnalysis.h"
> #include "llvm/Analysis/ValueTracking.h"
> @@ -504,7 +505,11 @@
> }
> }
>
> -void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) {
> +/// If RegPressure is non null, compute register pressure as a side
> effect. The
> +/// DAG builder is an efficient place to do it because it already visits
> +/// operands.
> +void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
> + RegPressureTracker *RPTracker) {
> // Create an SUnit for each real instruction.
> initSUnits();
>
> @@ -555,6 +560,10 @@
> PrevMI = MI;
> continue;
> }
> + if (RPTracker) {
> + RPTracker->recede();
> + assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find
> MI");
> + }
>
> assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel()
> &&
> "Cannot schedule terminators or labels!");
>
>
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