[llvm-commits] [llvm] r155188 - in /llvm/trunk/lib/Target: ARM/ CellSPU/ Hexagon/ MBlaze/ MSP430/ Mips/ PTX/ XCore/

[Craig Topper]

Now the next question is can I remove the emitting code without upsetting
out of tree targets.

On Friday, April 20, 2012, Jim Grosbach wrote:

> That makes sense. Given that they're in the header .inc like that, there's
> nothing that's even potentially taking advantage of forward declaring
> TargetRegisterClass in this context. Works for me. Thanks!
>
> -Jim
>
> On Apr 20, 2012, at 10:51 AM, Craig Topper <craig.topper at gmail.com> wrote:
>
> We were inconsistently using one or the other. The XXXRegClass is declared
> "extern" right next to XXXRegisterClass in the generated file so there
> shouldn't be any problem accessing XXXRegClass. The tablegen source says
> that XXXRegisterClass should be removed. Though its said that for 6 years.
>
> ~Craig
>
> On Fri, Apr 20, 2012 at 9:43 AM, Jim Grosbach <grosbach at apple.com> wrote:
>
> Hi Craig,
>
> What's the motivation here?
>
> With the previous definitions we could reference and pass around register
> classes without always needing to have the full definition of the class
> available until we actually wanted to do something non-trivial with them.
> This way, anyplace that needs to select a register class will need to have
> the full class definition included.
>
> -Jim
>
> On Apr 20, 2012, at 12:30 AM, Craig Topper <craig.topper at gmail.com> wrote:
>
> > Author: ctopper
> > Date: Fri Apr 20 02:30:17 2012
> > New Revision: 155188
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=155188&view=rev
> > Log:
> > Convert more uses of XXXRegisterClass to &XXXRegClass. No functional
> change since they are equivalent.
> >
> > Modified:
> >    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> >    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> >    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> >    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> >    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> >    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> >    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> >    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> >    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> >    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
> >    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
> >    llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
> >    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> >    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> >    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> >    llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> >    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
> >    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
> >    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> >    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> >    llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
> >    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
> >    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> >    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> >    llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
> >    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> >    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
> >    llvm/trunk/lib/Target/PTX/PTXMFInfoExtract.cpp
> >    llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp
> >    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> >    llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=155188&r1=155187&r2=155188&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Apr 20
> 02:30:17 2012
> > @@ -258,7 +258,7 @@
> >
> > const TargetRegisterClass *
> > ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
> > -  return ARM::GPRRegisterClass;
> > +  return &ARM::GPRRegClass;
> > }
> >
> > const TargetRegisterClass *
> > @@ -369,7 +369,7 @@
> >   };
> >
> >   // We only support even/odd hints for GPR
>
>

-- 
~Craig
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20120420/3286b533/attachment.html>