[llvm-commits] [llvm] r155002 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt

[Silviu Baranga]

Author: sbaranga
Date: Wed Apr 18 09:09:07 2012
New Revision: 155002

URL: http://llvm.org/viewvc/llvm-project?rev=155002&view=rev
Log:
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=155002&r1=155001&r2=155002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 18 09:09:07 2012
@@ -4646,22 +4646,32 @@
 //
 
 // Move to ARM core register from Special Register
-def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
+def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
               "mrs", "\t$Rd, apsr", []> {
   bits<4> Rd;
   let Inst{23-16} = 0b00001111;
+  let Unpredictable{19-17} = 0b111;
+
   let Inst{15-12} = Rd;
-  let Inst{7-4} = 0b0000;
+
+  let Inst{11-0} = 0b000000000000;
+  let Unpredictable{11-0} = 0b110100001111;
 }
 
-def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
+def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, Requires<[IsARM]>;
 
-def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
+// The MRSsys instruction is the MRS instruction from the ARM ARM,
+// section B9.3.9, with the R bit set to 1.
+def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
                  "mrs", "\t$Rd, spsr", []> {
   bits<4> Rd;
   let Inst{23-16} = 0b01001111;
+  let Unpredictable{19-16} = 0b1111;
+
   let Inst{15-12} = Rd;
-  let Inst{7-4} = 0b0000;
+
+  let Inst{11-0} = 0b000000000000;
+  let Unpredictable{11-0} = 0b110100001111;
 }
 
 // Move from ARM core register to Special Register

Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt?rev=155002&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt Wed Apr 18 09:09:07 2012
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x00 0xf0 0x0f 0x01
+0x00 0xf0 0x0f 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x00 0xf0 0x4f 0x01
+0x00 0xf0 0x4f 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x0f 0x0d 0x01 0x01
+0x0f 0x0d 0x01 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x0f 0x0d 0x40 0x01
+0x0f 0x0d 0x40 0x01
+