[llvm-commits] [llvm] r154816 - in /llvm/trunk: lib/CodeGen/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb2/ test/CodeGen/X86/ test/CodeGen/XCore/ test/Transforms/LoopStrengthReduce/X86/
Chandler Carruth
chandlerc at gmail.com
Mon Apr 16 06:49:17 PDT 2012
Author: chandlerc
Date: Mon Apr 16 08:49:17 2012
New Revision: 154816
URL: http://llvm.org/viewvc/llvm-project?rev=154816&view=rev
Log:
Flip the new block-placement pass to be on by default.
This is mostly to test the waters. I'd like to get results from FNT
build bots and other bots running on non-x86 platforms.
This feature has been pretty heavily tested over the last few months by
me, and it fixes several of the execution time regressions caused by the
inlining work by preventing inlining decisions from radically impacting
block layout.
I've seen very large improvements in yacr2 and ackermann benchmarks,
along with the expected noise across all of the benchmark suite whenever
code layout changes. I've analyzed all of the regressions and fixed
them, or found them to be impossible to fix. See my email to llvmdev for
more details.
I'd like for this to be in 3.1 as it complements the inliner changes,
but if any failures are showing up or anyone has concerns, it is just
a flag flip and so can be easily turned off.
I'm switching it on tonight to try and get at least one run through
various folks' performance suites in case SPEC or something else has
serious issues with it. I'll watch bots and revert if anything shows up.
Modified:
llvm/trunk/lib/CodeGen/Passes.cpp
llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
llvm/trunk/test/CodeGen/ARM/tail-opts.ll
llvm/trunk/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
llvm/trunk/test/CodeGen/Mips/eh.ll
llvm/trunk/test/CodeGen/Mips/fpbr.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll
llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
llvm/trunk/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
llvm/trunk/test/CodeGen/X86/block-placement.ll
llvm/trunk/test/CodeGen/X86/br-fold.ll
llvm/trunk/test/CodeGen/X86/call-push.ll
llvm/trunk/test/CodeGen/X86/licm-dominance.ll
llvm/trunk/test/CodeGen/X86/loop-blocks.ll
llvm/trunk/test/CodeGen/X86/machine-cp.ll
llvm/trunk/test/CodeGen/X86/postra-licm.ll
llvm/trunk/test/CodeGen/X86/pr2659.ll
llvm/trunk/test/CodeGen/X86/select.ll
llvm/trunk/test/CodeGen/X86/sibcall.ll
llvm/trunk/test/CodeGen/X86/sink-hoist.ll
llvm/trunk/test/CodeGen/X86/smul-with-overflow.ll
llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll
llvm/trunk/test/CodeGen/X86/switch-bt.ll
llvm/trunk/test/CodeGen/X86/tail-opts.ll
llvm/trunk/test/CodeGen/X86/uint64-to-float.ll
llvm/trunk/test/CodeGen/X86/xor-icmp.ll
llvm/trunk/test/CodeGen/XCore/ashr.ll
llvm/trunk/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Mon Apr 16 08:49:17 2012
@@ -37,8 +37,9 @@
cl::desc("Disable tail duplication"));
static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
cl::desc("Disable pre-register allocation tail duplication"));
-static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
- cl::Hidden, cl::desc("Enable probability-driven block placement"));
+static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
+ cl::Hidden, cl::desc("Disable the probability-driven block placement, and "
+ "re-enable the old code placement pass"));
static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
@@ -610,10 +611,10 @@
/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
AnalysisID ID = &NoPassID;
- if (EnableBlockPlacement) {
- // MachineBlockPlacement is an experimental pass which is disabled by
- // default currently. Eventually it should subsume CodePlacementOpt, so
- // when enabled, the other is disabled.
+ if (!DisableBlockPlacement) {
+ // MachineBlockPlacement is a new pass which subsumes the functionality of
+ // CodPlacementOpt. The old code placement pass can be restored by
+ // disabling block placement, but eventually it will be removed.
ID = addPass(MachineBlockPlacementID);
} else {
ID = addPass(CodePlacementOptID);
Modified: llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll Mon Apr 16 08:49:17 2012
@@ -26,7 +26,7 @@
; CHECK: bb2
; CHECK: subs [[REG:r[0-9]+]], #1
; CHECK: cmp [[REG]], #0
-; CHECK: bgt
+; CHECK: ble
%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
%tries.0 = sub i32 2147483647, %indvar
%tmp1 = icmp sgt i32 %tries.0, 0
Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Mon Apr 16 08:49:17 2012
@@ -16,11 +16,11 @@
; CHECK: tail_duplicate_me:
; CHECK: qux
-; CHECK: qux
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
; CHECK: str r
; CHECK-NEXT: bx r
+; CHECK: qux
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
; CHECK: str r
Modified: llvm/trunk/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/2009-01-01-BrCond.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/2009-01-01-BrCond.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/2009-01-01-BrCond.ll Mon Apr 16 08:49:17 2012
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=cellspu -o - | grep brnz
+; RUN: llc < %s -march=cellspu -o - | grep brz
; PR3274
target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
Modified: llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/analyzebranch.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/analyzebranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/analyzebranch.ll Mon Apr 16 08:49:17 2012
@@ -26,9 +26,9 @@
define void @f1(float %f) nounwind {
entry:
-; CHECK: bc1t $BB1_2
+; CHECK: bc1f $BB1_1
; CHECK: nop
-; CHECK: # BB#1:
+; CHECK: # BB#2:
%cmp = fcmp une float %f, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
Modified: llvm/trunk/test/CodeGen/Mips/eh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/eh.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/eh.ll Mon Apr 16 08:49:17 2012
@@ -26,7 +26,7 @@
lpad: ; preds = %entry
; CHECK-EL: # %lpad
; CHECK-EL: lw $gp
-; CHECK-EL: beq $5
+; CHECK-EL: bne $5
%exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
catch i8* bitcast (i8** @_ZTId to i8*)
Modified: llvm/trunk/test/CodeGen/Mips/fpbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpbr.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fpbr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fpbr.ll Mon Apr 16 08:49:17 2012
@@ -45,7 +45,7 @@
define void @func2(float %f2, float %f3) nounwind {
entry:
; CHECK: c.ole.s
-; CHECK: bc1f
+; CHECK: bc1t
%cmp = fcmp ugt float %f2, %f3
br i1 %cmp, label %if.else, label %if.then
@@ -102,7 +102,7 @@
define void @func5(double %f2, double %f3) nounwind {
entry:
; CHECK: c.ole.d
-; CHECK: bc1f
+; CHECK: bc1t
%cmp = fcmp ugt double %f2, %f3
br i1 %cmp, label %if.else, label %if.then
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll Mon Apr 16 08:49:17 2012
@@ -58,8 +58,8 @@
entry:
; CHECK: f4:
; CHECK: blo LBB
- %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
- br i1 %tmp, label %return, label %cond_true
+ %tmp = icmp uge i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
fence seq_cst
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Mon Apr 16 08:49:17 2012
@@ -29,13 +29,13 @@
define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
entry:
; CHECK: CountTree:
-; CHECK: it eq
-; CHECK: cmpeq
-; CHECK: bne
-; CHECK: cmp
; CHECK: itt eq
; CHECK: moveq
; CHECK: popeq
+; CHECK: bne
+; CHECK: cmp
+; CHECK: it eq
+; CHECK: cmpeq
br label %tailrecurse
tailrecurse: ; preds = %bb, %entry
@@ -83,7 +83,7 @@
entry:
; CHECK: t2:
; CHECK: cmp r0, #0
-; CHECK: beq
+; CHECK: bne
br i1 undef, label %bb.i.i3, label %growMapping.exit
bb.i.i3: ; preds = %entry
Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-jtb.ll Mon Apr 16 08:49:17 2012
@@ -3,11 +3,19 @@
; Do not use tbb / tbh if any destination is before the jumptable.
; rdar://7102917
-define i16 @main__getopt_internal_2E_exit_2E_ce(i32) nounwind {
+define i16 @main__getopt_internal_2E_exit_2E_ce(i32, i1 %b) nounwind {
+entry:
+ br i1 %b, label %codeRepl127.exitStub, label %newFuncRoot
+
newFuncRoot:
br label %_getopt_internal.exit.ce
codeRepl127.exitStub: ; preds = %_getopt_internal.exit.ce
+ ; Add an explicit edge back to before the jump table to ensure this block
+ ; is placed first.
+ br i1 %b, label %newFuncRoot, label %codeRepl127.exitStub.exit
+
+codeRepl127.exitStub.exit:
ret i16 0
parse_options.exit.loopexit.exitStub: ; preds = %_getopt_internal.exit.ce
Modified: llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll Mon Apr 16 08:49:17 2012
@@ -6,8 +6,8 @@
define i32 @test(i32 %argc, i8** %argv) nounwind {
entry:
; CHECK: cmpl $2
-; CHECK-NEXT: je
-; CHECK-NEXT: %entry
+; CHECK-NEXT: jne
+; CHECK-NEXT: %bb2
switch i32 %argc, label %UnifiedReturnBlock [
i32 1, label %bb
Modified: llvm/trunk/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll Mon Apr 16 08:49:17 2012
@@ -1,4 +1,4 @@
-; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jnp
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jp
; rdar://5902801
declare void @test2()
Modified: llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll Mon Apr 16 08:49:17 2012
@@ -17,7 +17,7 @@
; CHECK: andl $150
; CHECK-NEXT: testb
-; CHECK-NEXT: jg
+; CHECK-NEXT: jle
entry.if.end_crit_edge: ; preds = %entry
%tmp4.pre = load i32* @g_38 ; <i32> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Mon Apr 16 08:49:17 2012
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=i686-linux -enable-block-placement < %s | FileCheck %s
+; RUN: llc -mtriple=i686-linux < %s | FileCheck %s
declare void @error(i32 %i, i32 %a, i32 %b)
Modified: llvm/trunk/test/CodeGen/X86/br-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/br-fold.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/br-fold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/br-fold.ll Mon Apr 16 08:49:17 2012
@@ -1,7 +1,7 @@
; RUN: llc -march=x86-64 < %s | FileCheck %s
; CHECK: orq
-; CHECK-NEXT: jne
+; CHECK-NEXT: je
@_ZN11xercesc_2_513SchemaSymbols21fgURI_SCHEMAFORSCHEMAE = external constant [33 x i16], align 32 ; <[33 x i16]*> [#uses=1]
@_ZN11xercesc_2_56XMLUni16fgNotationStringE = external constant [9 x i16], align 16 ; <[9 x i16]*> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/call-push.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/call-push.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/call-push.ll (original)
+++ llvm/trunk/test/CodeGen/X86/call-push.ll Mon Apr 16 08:49:17 2012
@@ -7,8 +7,8 @@
; CHECK: decode_byte:
; CHECK: pushl
; CHECK: popl
-; CHECK: popl
; CHECK: jmp
+; CHECK: popl
entry:
%tmp2 = getelementptr %struct.decode_t* %decode, i32 0, i32 4 ; <i16*> [#uses=1]
%tmp23 = bitcast i16* %tmp2 to i32* ; <i32*> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/licm-dominance.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/licm-dominance.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/licm-dominance.ll (original)
+++ llvm/trunk/test/CodeGen/X86/licm-dominance.ll Mon Apr 16 08:49:17 2012
@@ -1,7 +1,7 @@
-; RUN: llc -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -asm-verbose=true < %s | FileCheck %s
; MachineLICM should check dominance before hoisting instructions.
-; CHECK: jne LBB0_3
+; CHECK: ## in Loop:
; CHECK-NEXT: xorb %al, %al
; CHECK-NEXT: testb %al, %al
Modified: llvm/trunk/test/CodeGen/X86/loop-blocks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-blocks.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/loop-blocks.ll (original)
+++ llvm/trunk/test/CodeGen/X86/loop-blocks.ll Mon Apr 16 08:49:17 2012
@@ -41,6 +41,7 @@
; CHECK-NEXT: align
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: callq bar99
+; CHECK-NEXT: align
; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: callq body
@@ -75,19 +76,21 @@
; CHECK: yet_more_involved:
; CHECK: jmp .LBB2_1
; CHECK-NEXT: align
-; CHECK-NEXT: .LBB2_4:
-; CHECK-NEXT: callq bar99
+; CHECK-NEXT: .LBB2_5:
+; CHECK-NEXT: callq block_a_true_func
+; CHECK-NEXT: callq block_a_merge_func
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB2_1:
+; CHECK-NEXT: callq body
+;
+; LBB2_4
+; CHECK: callq bar99
; CHECK-NEXT: callq get
; CHECK-NEXT: cmpl $2999, %eax
; CHECK-NEXT: jle .LBB2_5
; CHECK-NEXT: callq block_a_false_func
; CHECK-NEXT: callq block_a_merge_func
; CHECK-NEXT: jmp .LBB2_1
-; CHECK-NEXT: .LBB2_5:
-; CHECK-NEXT: callq block_a_true_func
-; CHECK-NEXT: callq block_a_merge_func
-; CHECK-NEXT: .LBB2_1:
-; CHECK-NEXT: callq body
define void @yet_more_involved() nounwind {
entry:
@@ -136,17 +139,22 @@
; CHECK-NEXT: align
; CHECK-NEXT: .LBB3_7:
; CHECK-NEXT: callq bar100
-; CHECK-NEXT: jmp .LBB3_1
-; CHECK-NEXT: .LBB3_8:
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB3_1:
+; CHECK-NEXT: callq loop_header
+; CHECK: jl .LBB3_7
+; CHECK: jge .LBB3_3
; CHECK-NEXT: callq bar101
; CHECK-NEXT: jmp .LBB3_1
-; CHECK-NEXT: .LBB3_9:
+; CHECK-NEXT: .LBB3_3:
+; CHECK: jge .LBB3_4
; CHECK-NEXT: callq bar102
; CHECK-NEXT: jmp .LBB3_1
-; CHECK-NEXT: .LBB3_5:
+; CHECK-NEXT: .LBB3_4:
+; CHECK: jl .LBB3_6
; CHECK-NEXT: callq loop_latch
-; CHECK-NEXT: .LBB3_1:
-; CHECK-NEXT: callq loop_header
+; CHECK-NEXT: jmp .LBB3_1
+; CHECK-NEXT: .LBB3_6:
define void @cfg_islands() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/X86/machine-cp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cp.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-cp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-cp.ll Mon Apr 16 08:49:17 2012
@@ -5,11 +5,11 @@
define i32 @t1(i32 %a, i32 %b) nounwind {
entry:
; CHECK: t1:
-; CHECK: jne
+; CHECK: je [[LABEL:.*BB.*]]
%cmp1 = icmp eq i32 %b, 0
br i1 %cmp1, label %while.end, label %while.body
-; CHECK: BB
+; CHECK: [[LABEL]]:
; CHECK-NOT: mov
; CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/postra-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/postra-licm.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/postra-licm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/postra-licm.ll Mon Apr 16 08:49:17 2012
@@ -70,8 +70,8 @@
bb23: ; preds = %imix_test.exit
unreachable
; Verify that there are no loads inside the loop.
-; X86-32: %bb26.preheader
; X86-32: .align 4
+; X86-32: %bb28
; X86-32-NOT: (%esp),
; X86-32-NOT: (%ebp),
; X86-32: jmp
Modified: llvm/trunk/test/CodeGen/X86/pr2659.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr2659.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr2659.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr2659.ll Mon Apr 16 08:49:17 2012
@@ -18,11 +18,12 @@
; CHECK-NOT: xorl
; CHECK-NOT: movl
; CHECK-NOT: LBB
-; CHECK: jne
+; CHECK: je
; There should be no moves required in the for loop body.
; CHECK: %forbody
; CHECK-NOT: mov
+; CHECK: jbe
ifthen: ; preds = %entry
ret i32 0
Modified: llvm/trunk/test/CodeGen/X86/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select.ll Mon Apr 16 08:49:17 2012
@@ -75,9 +75,9 @@
; Verify that the fmul gets sunk into the one part of the diamond where it is
; needed.
; CHECK: test6:
-; CHECK: jne
-; CHECK: mulps
+; CHECK: je
; CHECK: ret
+; CHECK: mulps
; CHECK: ret
}
Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sibcall.ll Mon Apr 16 08:49:17 2012
@@ -147,7 +147,7 @@
; 32: t11:
; 32-NOT: subl ${{[0-9]+}}, %esp
-; 32: jne
+; 32: je
; 32-NOT: movl
; 32-NOT: addl ${{[0-9]+}}, %esp
; 32: jmp {{_?}}foo5
Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sink-hoist.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sink-hoist.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sink-hoist.ll Mon Apr 16 08:49:17 2012
@@ -7,8 +7,9 @@
; CHECK: foo:
; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je
+; CHECK-NEXT: jne
; CHECK-NEXT: divsd
+; CHECK-NEXT: movaps
; CHECK-NEXT: ret
; CHECK: divsd
@@ -25,10 +26,10 @@
; CHECK: split:
; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je
-; CHECK-NEXT: divsd
+; CHECK-NEXT: jne
+; CHECK-NEXT: movaps
; CHECK-NEXT: ret
-; CHECK: movaps
+; CHECK: divsd
; CHECK-NEXT: ret
define double @split(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
Modified: llvm/trunk/test/CodeGen/X86/smul-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/smul-with-overflow.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/smul-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/smul-with-overflow.ll Mon Apr 16 08:49:17 2012
@@ -19,7 +19,7 @@
ret i1 false
; CHECK: test1:
; CHECK: imull
-; CHECK-NEXT: jo
+; CHECK-NEXT: jno
}
define i1 @test2(i32 %v1, i32 %v2) nounwind {
Modified: llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sub-with-overflow.ll Mon Apr 16 08:49:17 2012
@@ -20,7 +20,7 @@
; CHECK: func1:
; CHECK: subl 20(%esp)
-; CHECK-NEXT: jo
+; CHECK-NEXT: jno
}
define i1 @func2(i32 %v1, i32 %v2) nounwind {
@@ -40,7 +40,7 @@
; CHECK: func2:
; CHECK: subl 20(%esp)
-; CHECK-NEXT: jb
+; CHECK-NEXT: jae
}
declare i32 @printf(i8*, ...) nounwind
Modified: llvm/trunk/test/CodeGen/X86/switch-bt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-bt.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/switch-bt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/switch-bt.ll Mon Apr 16 08:49:17 2012
@@ -5,11 +5,11 @@
; CHECK: movabsq $2305843009482129440, %r
; CHECK-NEXT: btq %rax, %r
-; CHECK-NEXT: jb
-; CHECK-NEXT: movl $671088640, %e
+; CHECK-NEXT: jae
+; CHECK: movl $671088640, %e
; CHECK-NEXT: btq %rax, %r
-; CHECK-NEXT: jb
-; CHECK-NEXT: testq %rax, %r
+; CHECK-NEXT: jae
+; CHECK: testq %rax, %r
; CHECK-NEXT: j
define void @test(i8* %l) nounwind {
@@ -60,7 +60,7 @@
; CHECK-NEXT: movl $91
; CHECK-NOT: movl
; CHECK-NEXT: btl
-; CHECK-NEXT: jb
+; CHECK-NEXT: jae
entry:
switch i32 %x, label %if.end [
i32 6, label %if.then
@@ -85,7 +85,7 @@
; CHECK: cmpl $5
; CHECK: ja
; CHECK: cmpl $4
-; CHECK: jne
+; CHECK: je
switch i32 %x, label %if.end [
i32 0, label %if.then
i32 1, label %if.then
Modified: llvm/trunk/test/CodeGen/X86/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-opts.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-opts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-opts.ll Mon Apr 16 08:49:17 2012
@@ -113,15 +113,16 @@
; CHECK-NEXT: jbe .LBB2_3
; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: ja .LBB2_4
-; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT: movb $1, %al
-; CHECK-NEXT: ret
+; CHECK-NEXT: jmp .LBB2_2
; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_2
; CHECK-NEXT: .LBB2_4:
; CHECK-NEXT: xorb %al, %al
; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: ret
define i1 @dont_merge_oddly(float* %result) nounwind {
entry:
@@ -336,10 +337,10 @@
; CHECK: two:
; CHECK-NOT: XYZ
+; CHECK: ret
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $1, XYZ(%rip)
; CHECK-NOT: XYZ
-; CHECK: ret
define void @two() nounwind optsize {
entry:
Modified: llvm/trunk/test/CodeGen/X86/uint64-to-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/uint64-to-float.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/uint64-to-float.ll (original)
+++ llvm/trunk/test/CodeGen/X86/uint64-to-float.ll Mon Apr 16 08:49:17 2012
@@ -7,13 +7,14 @@
target triple = "x86_64-apple-darwin10.0.0"
; CHECK: testq %rdi, %rdi
-; CHECK-NEXT: jns LBB0_2
+; CHECK-NEXT: js LBB0_1
+; CHECK: cvtsi2ss
+; CHECK-NEXT: ret
+; CHECK: LBB0_1
; CHECK: shrq
; CHECK-NEXT: andq
; CHECK-NEXT: orq
; CHECK-NEXT: cvtsi2ss
-; CHECK: LBB0_2
-; CHECK-NEXT: cvtsi2ss
define float @test(i64 %a) {
entry:
%b = uitofp i64 %a to float
Modified: llvm/trunk/test/CodeGen/X86/xor-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-icmp.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor-icmp.ll Mon Apr 16 08:49:17 2012
@@ -9,13 +9,13 @@
; X32-NOT: andb
; X32-NOT: shrb
; X32: testb $64
-; X32: jne
+; X32: je
; X64: t:
; X64-NOT: setne
; X64: xorl
; X64: testb $64
-; X64: jne
+; X64: je
%0 = and i32 %a, 16384
%1 = icmp ne i32 %0, 0
%2 = and i32 %b, 16384
@@ -43,7 +43,7 @@
; X32: cmpl
; X32: sete
; X32-NOT: xor
-; X32: jne
+; X32: je
; X64: t2:
; X64: testl
@@ -51,7 +51,7 @@
; X64: testl
; X64: sete
; X64-NOT: xor
-; X64: jne
+; X64: je
entry:
%0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
%1 = icmp eq i32 %y, 0 ; <i1> [#uses=1]
Modified: llvm/trunk/test/CodeGen/XCore/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/ashr.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/ashr.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/ashr.ll Mon Apr 16 08:49:17 2012
@@ -30,7 +30,7 @@
}
; CHECK: f1:
; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
+; CHECK-NEXT: bt r0
define i32 @f2(i32 %a) {
%1 = icmp sge i32 %a, 0
@@ -51,9 +51,9 @@
}
; CHECK: f3:
; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
-; CHECK-NEXT: ldc r0, 10
-; CHECK: ldc r0, 17
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 17
+; CHECK: ldc r0, 10
define i32 @f4(i32 %a) {
%1 = icmp sge i32 %a, 0
@@ -62,9 +62,9 @@
}
; CHECK: f4:
; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
-; CHECK-NEXT: ldc r0, 17
-; CHECK: ldc r0, 10
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 10
+; CHECK: ldc r0, 17
define i32 @f5(i32 %a) {
%1 = icmp sge i32 %a, 0
Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll?rev=154816&r1=154815&r2=154816&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll Mon Apr 16 08:49:17 2012
@@ -61,7 +61,7 @@
; CHECK: @test2
; CHECK: %entry
; CHECK-NOT: mov
-; CHECK: jne
+; CHECK: je
define void @test2(i32 %n) nounwind uwtable {
entry:
br i1 undef, label %while.end, label %for.cond468
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