[llvm-commits] [PATCH 10/11] (patch) Mips specific inline asm: constraint 'c'

[Jack Carter]

A register suitable for use in an indirect
jump. This will always be $25 for -mabicalls

Even thought this example doesn't use and indirec jump the
destination and source register should be $25:

#define _mips_addi(rs,val) __extension__({ \
    int __s = (rs), __v = (val); \
    int __t; \
    __asm__ __volatile__( \
         "addi %0,%1,%2" \
	     : "=c" (__t) \
	     : "c" (rs), "I" (__v)); \
    __t; \
})
---
 lib/Target/Mips/MipsISelLowering.cpp       |   14 +++++++++++++-
 test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll |   12 +++++++-----
 2 files changed, 20 insertions(+), 6 deletions(-)

-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index bf0779e..cac819e 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2886,13 +2886,15 @@ getConstraintType(const std::string &Constraint) const
   //       unless generating MIPS16 code.
   // 'y' : Equivalent to r; retained for
   //       backwards compatibility.
-  // 'f' : Floating Point registers.
+  // 'c' : A register suitable for use in an indirect
+  //       jump. This will always be $25 for -mabicalls.
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
       default : break;
       case 'd':
       case 'y':
       case 'f':
+      case 'c':
         return C_RegisterClass;
     }
   }
@@ -2926,6 +2928,10 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
     if (type->isFloatTy())
       weight = CW_Register;
     break;
+  case 'c': // $25 for indirect jumps
+      if (type->isIntegerTy())
+      weight = CW_SpecificReg;
+      break;
   case 'I': // signed 16 bit immediate
   case 'J': // integer zero
   case 'K': // unsigned 16 bit immediate
@@ -2966,6 +2972,12 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
         else
           return std::make_pair(0U, Mips::AFGR64RegisterClass);
       }
+      break;
+    case 'c': // register suitable for indirect jump
+      if (VT == MVT::i32)
+        return std::make_pair((unsigned)Mips::T9, Mips::CPURegsRegisterClass);
+      assert(VT == MVT::i64 && "Unexpected type.");
+      return std::make_pair((unsigned)Mips::T9_64, Mips::CPU64RegsRegisterClass);
     }
   }
   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
index 9527719..e6fe14c 100644
--- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
@@ -1,10 +1,7 @@
-;
-;Register constraint "r" should take both ints and shorts.
-;
+; Positive test for inline register constraints
 ;
 ; RUN: llc -march=mipsel < %s 
 
-
 define i32 @main() nounwind {
 entry:
 
@@ -26,6 +23,11 @@ entry:
 ;CHECK:	#NO_APP
   tail call i32 asm "add $0,$1,$2", "=r,r,r,0"(i32 7, i32 8, i32 0) nounwind
 
+; Now c with 1024: make sure register $25 is picked
+; CHECK: #APP
+; CHECK: addi $25,${{[0-9]+}},1024
+; CHECK: #NO_APP	
+   tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
+
   ret i32 0
 }
-