[llvm-commits] [llvm] r154544 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt

[Kevin Enderby]

Author: enderby
Date: Wed Apr 11 17:40:17 2012
New Revision: 154544

URL: http://llvm.org/viewvc/llvm-project?rev=154544&view=rev
Log:
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=154544&r1=154543&r2=154544&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Apr 11 17:40:17 2012
@@ -2410,6 +2410,8 @@
     case ARM::VST2b8wb_register:
     case ARM::VST2b16wb_register:
     case ARM::VST2b32wb_register:
+      if (Rm == 0xF)
+        return MCDisassembler::Fail;
       Inst.addOperand(MCOperand::CreateImm(0));
       break;
     case ARM::VST3d8_UPD:

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt?rev=154544&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt Wed Apr 11 17:40:17 2012
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.391 VST1 (multiple single elements)
+# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128]
+# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
+# contains two or four registers.  rdar://11220250
+0x00 0xf9 0x2f 0x06