[llvm-commits] [llvm] r154459 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neon.txt test/MC/Disassembler/ARM/neont2.txt
Kevin Enderby
enderby at apple.com
Tue Apr 10 17:25:40 PDT 2012
Author: enderby
Date: Tue Apr 10 19:25:40 2012
New Revision: 154459
URL: http://llvm.org/viewvc/llvm-project?rev=154459&view=rev
Log:
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/neon.txt
llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=154459&r1=154458&r2=154459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Apr 10 19:25:40 2012
@@ -2262,6 +2262,8 @@
case ARM::VLD2b8wb_register:
case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_register:
+ Inst.addOperand(MCOperand::CreateImm(0));
+ break;
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
case ARM::VLD3d32_UPD:
@@ -2330,6 +2332,16 @@
!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
break;
+ case ARM::VLD2d8wb_fixed:
+ case ARM::VLD2d16wb_fixed:
+ case ARM::VLD2d32wb_fixed:
+ case ARM::VLD2b8wb_fixed:
+ case ARM::VLD2b16wb_fixed:
+ case ARM::VLD2b32wb_fixed:
+ case ARM::VLD2q8wb_fixed:
+ case ARM::VLD2q16wb_fixed:
+ case ARM::VLD2q32wb_fixed:
+ break;
}
return S;
Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=154459&r1=154458&r2=154459&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Tue Apr 10 19:25:40 2012
@@ -2061,3 +2061,185 @@
# CHECK: vst4.16 {d8, d10, d12, d14}, [r4]
0x8f 0x81 0x04 0xf4
# CHECK: vst4.32 {d8, d10, d12, d14}, [r4]
+
+# rdar://11204059
+0x0d 0x87 0x24 0xf4
+# CHECK: vld1.8 {d8}, [r4]!
+0x4d 0x87 0x24 0xf4
+# CHECK: vld1.16 {d8}, [r4]!
+0x8d 0x87 0x24 0xf4
+# CHECK: vld1.32 {d8}, [r4]!
+0xcd 0x87 0x24 0xf4
+# CHECK: vld1.64 {d8}, [r4]!
+0x06 0x87 0x24 0xf4
+# CHECK: vld1.8 {d8}, [r4], r6
+0x46 0x87 0x24 0xf4
+# CHECK: vld1.16 {d8}, [r4], r6
+0x86 0x87 0x24 0xf4
+# CHECK: vld1.32 {d8}, [r4], r6
+0xc6 0x87 0x24 0xf4
+# CHECK: vld1.64 {d8}, [r4], r6
+0x0d 0x8a 0x24 0xf4
+# CHECK: vld1.8 {d8, d9}, [r4]!
+0x4d 0x8a 0x24 0xf4
+# CHECK: vld1.16 {d8, d9}, [r4]!
+0x8d 0x8a 0x24 0xf4
+# CHECK: vld1.32 {d8, d9}, [r4]!
+0xcd 0x8a 0x24 0xf4
+# CHECK: vld1.64 {d8, d9}, [r4]!
+0x06 0x8a 0x24 0xf4
+# CHECK: vld1.8 {d8, d9}, [r4], r6
+0x46 0x8a 0x24 0xf4
+# CHECK: vld1.16 {d8, d9}, [r4], r6
+0x86 0x8a 0x24 0xf4
+# CHECK: vld1.32 {d8, d9}, [r4], r6
+0xc6 0x8a 0x24 0xf4
+# CHECK: vld1.64 {d8, d9}, [r4], r6
+0x0d 0x86 0x24 0xf4
+# CHECK: vld1.8 {d8, d9, d10}, [r4]!
+0x4d 0x86 0x24 0xf4
+# CHECK: vld1.16 {d8, d9, d10}, [r4]!
+0x8d 0x86 0x24 0xf4
+# CHECK: vld1.32 {d8, d9, d10}, [r4]!
+0xcd 0x86 0x24 0xf4
+# CHECK: vld1.64 {d8, d9, d10}, [r4]!
+0x06 0x86 0x24 0xf4
+# CHECK: vld1.8 {d8, d9, d10}, [r4], r6
+0x46 0x86 0x24 0xf4
+# CHECK: vld1.16 {d8, d9, d10}, [r4], r6
+0x86 0x86 0x24 0xf4
+# CHECK: vld1.32 {d8, d9, d10}, [r4], r6
+0xc6 0x86 0x24 0xf4
+# CHECK: vld1.64 {d8, d9, d10}, [r4], r6
+0x0d 0x82 0x24 0xf4
+# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]!
+0x4d 0x82 0x24 0xf4
+# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]!
+0x8d 0x82 0x24 0xf4
+# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]!
+0xcd 0x82 0x24 0xf4
+# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]!
+0x06 0x82 0x24 0xf4
+# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6
+0x46 0x82 0x24 0xf4
+# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6
+0x86 0x82 0x24 0xf4
+# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6
+0xc6 0x82 0x24 0xf4
+# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6
+0x0d 0x88 0x24 0xf4
+# CHECK: vld2.8 {d8, d9}, [r4]!
+0x4d 0x88 0x24 0xf4
+# CHECK: vld2.16 {d8, d9}, [r4]!
+0x8d 0x88 0x24 0xf4
+# CHECK: vld2.32 {d8, d9}, [r4]!
+0x06 0x88 0x24 0xf4
+# CHECK: vld2.8 {d8, d9}, [r4], r6
+0x46 0x88 0x24 0xf4
+# CHECK: vld2.16 {d8, d9}, [r4], r6
+0x86 0x88 0x24 0xf4
+# CHECK: vld2.32 {d8, d9}, [r4], r6
+0x0d 0x89 0x24 0xf4
+# CHECK: vld2.8 {d8, d10}, [r4]!
+0x4d 0x89 0x24 0xf4
+# CHECK: vld2.16 {d8, d10}, [r4]!
+0x8d 0x89 0x24 0xf4
+# CHECK: vld2.32 {d8, d10}, [r4]!
+0x06 0x89 0x24 0xf4
+# CHECK: vld2.8 {d8, d10}, [r4], r6
+0x46 0x89 0x24 0xf4
+# CHECK: vld2.16 {d8, d10}, [r4], r6
+0x86 0x89 0x24 0xf4
+# CHECK: vld2.32 {d8, d10}, [r4], r6
+0x0d 0x84 0x24 0xf4
+# CHECK: vld3.8 {d8, d9, d10}, [r4]!
+0x4d 0x84 0x24 0xf4
+# CHECK: vld3.16 {d8, d9, d10}, [r4]!
+0x8d 0x84 0x24 0xf4
+# CHECK: vld3.32 {d8, d9, d10}, [r4]!
+0x06 0x85 0x24 0xf4
+# CHECK: vld3.8 {d8, d10, d12}, [r4], r6
+0x46 0x85 0x24 0xf4
+# CHECK: vld3.16 {d8, d10, d12}, [r4], r6
+0x86 0x85 0x24 0xf4
+# CHECK: vld3.32 {d8, d10, d12}, [r4], r6
+0x0d 0x80 0x24 0xf4
+# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]!
+0x4d 0x80 0x24 0xf4
+# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]!
+0x8d 0x80 0x24 0xf4
+# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]!
+0x06 0x81 0x24 0xf4
+# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6
+0x46 0x81 0x24 0xf4
+# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6
+0x86 0x81 0x24 0xf4
+# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6
+0x4f 0x8a 0x24 0xf4
+# CHECK: vld1.16 {d8, d9}, [r4]
+0x8f 0x8a 0x24 0xf4
+# CHECK: vld1.32 {d8, d9}, [r4]
+0xcf 0x8a 0x24 0xf4
+# CHECK: vld1.64 {d8, d9}, [r4]
+0x0f 0x8a 0x24 0xf4
+# CHECK: vld1.8 {d8, d9}, [r4]
+0x4f 0x88 0x24 0xf4
+# CHECK: vld2.16 {d8, d9}, [r4]
+0x8f 0x88 0x24 0xf4
+# CHECK: vld2.32 {d8, d9}, [r4]
+0x0f 0x88 0x24 0xf4
+# CHECK: vld2.8 {d8, d9}, [r4]
+0x4d 0x88 0x24 0xf4
+# CHECK: vld2.16 {d8, d9}, [r4]!
+0x46 0x88 0x24 0xf4
+# CHECK: vld2.16 {d8, d9}, [r4], r6
+0x8d 0x88 0x24 0xf4
+# CHECK: vld2.32 {d8, d9}, [r4]!
+0x86 0x88 0x24 0xf4
+# CHECK: vld2.32 {d8, d9}, [r4], r6
+0x0d 0x88 0x24 0xf4
+# CHECK: vld2.8 {d8, d9}, [r4]!
+0x06 0x88 0x24 0xf4
+# CHECK: vld2.8 {d8, d9}, [r4], r6
+0x4f 0x89 0x24 0xf4
+# CHECK: vld2.16 {d8, d10}, [r4]
+0x8f 0x89 0x24 0xf4
+# CHECK: vld2.32 {d8, d10}, [r4]
+0x0f 0x89 0x24 0xf4
+# CHECK: vld2.8 {d8, d10}, [r4]
+0x4d 0x83 0x24 0xf4
+# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]!
+0x46 0x83 0x24 0xf4
+# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6
+0x8d 0x83 0x24 0xf4
+# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]!
+0x86 0x83 0x24 0xf4
+# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6
+0x0d 0x83 0x24 0xf4
+# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]!
+0x06 0x83 0x24 0xf4
+# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6
+0x0f 0x84 0x24 0xf4
+# CHECK: vld3.8 {d8, d9, d10}, [r4]
+0x4f 0x84 0x24 0xf4
+# CHECK: vld3.16 {d8, d9, d10}, [r4]
+0x8f 0x84 0x24 0xf4
+# CHECK: vld3.32 {d8, d9, d10}, [r4]
+0x0f 0x80 0x24 0xf4
+# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]
+0x4f 0x80 0x24 0xf4
+# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]
+0x8f 0x80 0x24 0xf4
+# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]
+0x0f 0x85 0x24 0xf4
+# CHECK: vld3.8 {d8, d10, d12}, [r4]
+0x4f 0x85 0x24 0xf4
+# CHECK: vld3.16 {d8, d10, d12}, [r4]
+0x8f 0x85 0x24 0xf4
+# CHECK: vld3.32 {d8, d10, d12}, [r4]
+0x0f 0x81 0x24 0xf4
+# CHECK: vld4.8 {d8, d10, d12, d14}, [r4]
+0x4f 0x81 0x24 0xf4
+# CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
+0x8f 0x81 0x24 0xf4
+# CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=154459&r1=154458&r2=154459&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Tue Apr 10 19:25:40 2012
@@ -1778,3 +1778,185 @@
# CHECK: vst4.16 {d8, d10, d12, d14}, [r4]
0x04 0xf9 0x8f 0x81
# CHECK: vst4.32 {d8, d10, d12, d14}, [r4]
+
+# rdar://11204059
+0x24 0xf9 0x0d 0x87
+# CHECK: vld1.8 {d8}, [r4]!
+0x24 0xf9 0x4d 0x87
+# CHECK: vld1.16 {d8}, [r4]!
+0x24 0xf9 0x8d 0x87
+# CHECK: vld1.32 {d8}, [r4]!
+0x24 0xf9 0xcd 0x87
+# CHECK: vld1.64 {d8}, [r4]!
+0x24 0xf9 0x06 0x87
+# CHECK: vld1.8 {d8}, [r4], r6
+0x24 0xf9 0x46 0x87
+# CHECK: vld1.16 {d8}, [r4], r6
+0x24 0xf9 0x86 0x87
+# CHECK: vld1.32 {d8}, [r4], r6
+0x24 0xf9 0xc6 0x87
+# CHECK: vld1.64 {d8}, [r4], r6
+0x24 0xf9 0x0d 0x8a
+# CHECK: vld1.8 {d8, d9}, [r4]!
+0x24 0xf9 0x4d 0x8a
+# CHECK: vld1.16 {d8, d9}, [r4]!
+0x24 0xf9 0x8d 0x8a
+# CHECK: vld1.32 {d8, d9}, [r4]!
+0x24 0xf9 0xcd 0x8a
+# CHECK: vld1.64 {d8, d9}, [r4]!
+0x24 0xf9 0x06 0x8a
+# CHECK: vld1.8 {d8, d9}, [r4], r6
+0x24 0xf9 0x46 0x8a
+# CHECK: vld1.16 {d8, d9}, [r4], r6
+0x24 0xf9 0x86 0x8a
+# CHECK: vld1.32 {d8, d9}, [r4], r6
+0x24 0xf9 0xc6 0x8a
+# CHECK: vld1.64 {d8, d9}, [r4], r6
+0x24 0xf9 0x0d 0x86
+# CHECK: vld1.8 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x4d 0x86
+# CHECK: vld1.16 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x8d 0x86
+# CHECK: vld1.32 {d8, d9, d10}, [r4]!
+0x24 0xf9 0xcd 0x86
+# CHECK: vld1.64 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x06 0x86
+# CHECK: vld1.8 {d8, d9, d10}, [r4], r6
+0x24 0xf9 0x46 0x86
+# CHECK: vld1.16 {d8, d9, d10}, [r4], r6
+0x24 0xf9 0x86 0x86
+# CHECK: vld1.32 {d8, d9, d10}, [r4], r6
+0x24 0xf9 0xc6 0x86
+# CHECK: vld1.64 {d8, d9, d10}, [r4], r6
+0x24 0xf9 0x0d 0x82
+# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x4d 0x82
+# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x8d 0x82
+# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0xcd 0x82
+# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x06 0x82
+# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x46 0x82
+# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x86 0x82
+# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0xc6 0x82
+# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x0d 0x88
+# CHECK: vld2.8 {d8, d9}, [r4]!
+0x24 0xf9 0x4d 0x88
+# CHECK: vld2.16 {d8, d9}, [r4]!
+0x24 0xf9 0x8d 0x88
+# CHECK: vld2.32 {d8, d9}, [r4]!
+0x24 0xf9 0x06 0x88
+# CHECK: vld2.8 {d8, d9}, [r4], r6
+0x24 0xf9 0x46 0x88
+# CHECK: vld2.16 {d8, d9}, [r4], r6
+0x24 0xf9 0x86 0x88
+# CHECK: vld2.32 {d8, d9}, [r4], r6
+0x24 0xf9 0x0d 0x89
+# CHECK: vld2.8 {d8, d10}, [r4]!
+0x24 0xf9 0x4d 0x89
+# CHECK: vld2.16 {d8, d10}, [r4]!
+0x24 0xf9 0x8d 0x89
+# CHECK: vld2.32 {d8, d10}, [r4]!
+0x24 0xf9 0x06 0x89
+# CHECK: vld2.8 {d8, d10}, [r4], r6
+0x24 0xf9 0x46 0x89
+# CHECK: vld2.16 {d8, d10}, [r4], r6
+0x24 0xf9 0x86 0x89
+# CHECK: vld2.32 {d8, d10}, [r4], r6
+0x24 0xf9 0x0d 0x84
+# CHECK: vld3.8 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x4d 0x84
+# CHECK: vld3.16 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x8d 0x84
+# CHECK: vld3.32 {d8, d9, d10}, [r4]!
+0x24 0xf9 0x06 0x85
+# CHECK: vld3.8 {d8, d10, d12}, [r4], r6
+0x24 0xf9 0x46 0x85
+# CHECK: vld3.16 {d8, d10, d12}, [r4], r6
+0x24 0xf9 0x86 0x85
+# CHECK: vld3.32 {d8, d10, d12}, [r4], r6
+0x24 0xf9 0x0d 0x80
+# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x4d 0x80
+# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x8d 0x80
+# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x06 0x81
+# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6
+0x24 0xf9 0x46 0x81
+# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6
+0x24 0xf9 0x86 0x81
+# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6
+0x24 0xf9 0x4f 0x8a
+# CHECK: vld1.16 {d8, d9}, [r4]
+0x24 0xf9 0x8f 0x8a
+# CHECK: vld1.32 {d8, d9}, [r4]
+0x24 0xf9 0xcf 0x8a
+# CHECK: vld1.64 {d8, d9}, [r4]
+0x24 0xf9 0x0f 0x8a
+# CHECK: vld1.8 {d8, d9}, [r4]
+0x24 0xf9 0x4f 0x88
+# CHECK: vld2.16 {d8, d9}, [r4]
+0x24 0xf9 0x8f 0x88
+# CHECK: vld2.32 {d8, d9}, [r4]
+0x24 0xf9 0x0f 0x88
+# CHECK: vld2.8 {d8, d9}, [r4]
+0x24 0xf9 0x4d 0x88
+# CHECK: vld2.16 {d8, d9}, [r4]!
+0x24 0xf9 0x46 0x88
+# CHECK: vld2.16 {d8, d9}, [r4], r6
+0x24 0xf9 0x8d 0x88
+# CHECK: vld2.32 {d8, d9}, [r4]!
+0x24 0xf9 0x86 0x88
+# CHECK: vld2.32 {d8, d9}, [r4], r6
+0x24 0xf9 0x0d 0x88
+# CHECK: vld2.8 {d8, d9}, [r4]!
+0x24 0xf9 0x06 0x88
+# CHECK: vld2.8 {d8, d9}, [r4], r6
+0x24 0xf9 0x4f 0x89
+# CHECK: vld2.16 {d8, d10}, [r4]
+0x24 0xf9 0x8f 0x89
+# CHECK: vld2.32 {d8, d10}, [r4]
+0x24 0xf9 0x0f 0x89
+# CHECK: vld2.8 {d8, d10}, [r4]
+0x24 0xf9 0x4d 0x83
+# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x46 0x83
+# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x8d 0x83
+# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x86 0x83
+# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x0d 0x83
+# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]!
+0x24 0xf9 0x06 0x83
+# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6
+0x24 0xf9 0x0f 0x84
+# CHECK: vld3.8 {d8, d9, d10}, [r4]
+0x24 0xf9 0x4f 0x84
+# CHECK: vld3.16 {d8, d9, d10}, [r4]
+0x24 0xf9 0x8f 0x84
+# CHECK: vld3.32 {d8, d9, d10}, [r4]
+0x24 0xf9 0x0f 0x80
+# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]
+0x24 0xf9 0x4f 0x80
+# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]
+0x24 0xf9 0x8f 0x80
+# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]
+0x24 0xf9 0x0f 0x85
+# CHECK: vld3.8 {d8, d10, d12}, [r4]
+0x24 0xf9 0x4f 0x85
+# CHECK: vld3.16 {d8, d10, d12}, [r4]
+0x24 0xf9 0x8f 0x85
+# CHECK: vld3.32 {d8, d10, d12}, [r4]
+0x24 0xf9 0x0f 0x81
+# CHECK: vld4.8 {d8, d10, d12, d14}, [r4]
+0x24 0xf9 0x4f 0x81
+# CHECK: vld4.16 {d8, d10, d12, d14}, [r4]
+0x24 0xf9 0x8f 0x81
+# CHECK: vld4.32 {d8, d10, d12, d14}, [r4]
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