[llvm-commits] [llvm] r154038 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/global-address.ll test/CodeGen/Mips/mips64fpldst.ll test/CodeGen/Mips/mips64intldst.ll
Akira Hatanaka
ahatanaka at mips.com
Wed Apr 4 12:02:38 PDT 2012
Author: ahatanak
Date: Wed Apr 4 14:02:38 2012
New Revision: 154038
URL: http://llvm.org/viewvc/llvm-project?rev=154038&view=rev
Log:
Fix LowerGlobalAddress to produce instructions with the correct relocation
types for N32 ABI. Add new test case and update existing ones.
Added:
llvm/trunk/test/CodeGen/Mips/global-address.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
llvm/trunk/test/CodeGen/Mips/mips64intldst.ll
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=154038&r1=154037&r2=154038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Apr 4 14:02:38 2012
@@ -1543,7 +1543,7 @@
EVT ValTy = Op.getValueType();
bool HasGotOfst = (GV->hasInternalLinkage() ||
(GV->hasLocalLinkage() && !isa<Function>(GV)));
- unsigned GotFlag = IsN64 ?
+ unsigned GotFlag = HasMips64 ?
(HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
(HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
@@ -1555,8 +1555,8 @@
if (!HasGotOfst)
return ResNode;
SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
- IsN64 ? MipsII::MO_GOT_OFST :
- MipsII::MO_ABS_LO);
+ HasMips64 ? MipsII::MO_GOT_OFST :
+ MipsII::MO_ABS_LO);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
}
Added: llvm/trunk/test/CodeGen/Mips/global-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/global-address.ll?rev=154038&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/global-address.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/global-address.ll Wed Apr 4 14:02:38 2012
@@ -0,0 +1,46 @@
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
+; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
+
+ at s1 = internal unnamed_addr global i32 8, align 4
+ at g1 = external global i32
+
+define void @foo() nounwind {
+entry:
+; PIC-O32: lw $[[R0:[0-9]+]], %got(s1)
+; PIC-O32: lw ${{[0-9]+}}, %lo(s1)($[[R0]])
+; PIC-O32: lw ${{[0-9]+}}, %got(g1)
+; STATIC-O32: lui $[[R1:[0-9]+]], %hi(s1)
+; STATIC-O32: lw ${{[0-9]+}}, %lo(s1)($[[R1]])
+; STATIC-O32: lui $[[R2:[0-9]+]], %hi(g1)
+; STATIC-O32: lw ${{[0-9]+}}, %lo(g1)($[[R2]])
+
+; PIC-N32: lw $[[R0:[0-9]+]], %got_page(s1)
+; PIC-N32: lw ${{[0-9]+}}, %got_ofst(s1)($[[R0]])
+; PIC-N32: lw ${{[0-9]+}}, %got_disp(g1)
+; STATIC-N32: lui $[[R1:[0-9]+]], %hi(s1)
+; STATIC-N32: lw ${{[0-9]+}}, %lo(s1)($[[R1]])
+; STATIC-N32: lui $[[R2:[0-9]+]], %hi(g1)
+; STATIC-N32: lw ${{[0-9]+}}, %lo(g1)($[[R2]])
+
+; PIC-N64: ld $[[R0:[0-9]+]], %got_page(s1)
+; PIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R0]])
+; PIC-N64: ld ${{[0-9]+}}, %got_disp(g1)
+; STATIC-N64: ld $[[R1:[0-9]+]], %got_page(s1)
+; STATIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R1]])
+; STATIC-N64: ld ${{[0-9]+}}, %got_disp(g1)
+
+ %0 = load i32* @s1, align 4
+ tail call void @foo1(i32 %0) nounwind
+ %1 = load i32* @g1, align 4
+ store i32 %1, i32* @s1, align 4
+ %add = add nsw i32 %1, 2
+ store i32 %add, i32* @g1, align 4
+ ret void
+}
+
+declare void @foo1(i32)
+
Modified: llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll?rev=154038&r1=154037&r2=154038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll Wed Apr 4 14:02:38 2012
@@ -12,7 +12,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfl1
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load float* @f0, align 4
ret float %0
@@ -24,7 +24,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfl2
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load double* @d0, align 8
ret double %0
@@ -36,7 +36,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfs1
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load float* @f1, align 4
store float %0, float* @f0, align 4
@@ -49,7 +49,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
; CHECK-N32: funcfs2
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
%0 = load double* @d1, align 8
store double %0, double* @d0, align 8
Modified: llvm/trunk/test/CodeGen/Mips/mips64intldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64intldst.ll?rev=154038&r1=154037&r2=154038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64intldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64intldst.ll Wed Apr 4 14:02:38 2012
@@ -16,7 +16,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: func1
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(c)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]])
%0 = load i8* @c, align 4
%conv = sext i8 %0 to i64
@@ -29,7 +29,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: func2
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(s)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]])
%0 = load i16* @s, align 4
%conv = sext i16 %0 to i64
@@ -42,7 +42,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: func3
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(i)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]])
%0 = load i32* @i, align 4
%conv = sext i32 %0 to i64
@@ -55,7 +55,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: func4
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(l)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]])
%0 = load i64* @l, align 8
ret i64 %0
@@ -67,7 +67,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc)
; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: ufunc1
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(uc)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc)
; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
%0 = load i8* @uc, align 4
%conv = zext i8 %0 to i64
@@ -80,7 +80,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us)
; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: ufunc2
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(us)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us)
; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
%0 = load i16* @us, align 4
%conv = zext i16 %0 to i64
@@ -93,7 +93,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui)
; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: ufunc3
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(ui)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui)
; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
%0 = load i32* @ui, align 4
%conv = zext i32 %0 to i64
@@ -106,7 +106,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: sfunc1
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(c)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]])
%0 = load i64* @l1, align 8
%conv = trunc i64 %0 to i8
@@ -120,7 +120,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: sfunc2
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(s)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]])
%0 = load i64* @l1, align 8
%conv = trunc i64 %0 to i16
@@ -134,7 +134,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: sfunc3
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(i)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]])
%0 = load i64* @l1, align 8
%conv = trunc i64 %0 to i32
@@ -148,7 +148,7 @@
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]])
; CHECK-N32: sfunc4
-; CHECK-N32: lw $[[R0:[0-9]+]], %got(l)
+; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]])
%0 = load i64* @l1, align 8
store i64 %0, i64* @l, align 8
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