[llvm-commits] [patch]Fix for TableGen decoder generator

[Silviu Baranga]

I only applied the patch to the test folder in 153874.
I've committed the rest of the changes in 153875.

Thanks,
Silviu

> -----Original Message-----
> From: Silviu Baranga [mailto:silbar01 at arm.com]
> Sent: 02 April 2012 16:33
> To: 'Joel Jones'; llvm-commits at cs.uiuc.edu LLVM
> Cc: dblaikie at gmail.com
> Subject: RE: [llvm-commits] [patch]Fix for TableGen decoder generator
> 
> Committed in 153874.
> 
> On Apr 2, 2012, at 15:18, Joel Jones wrote:
> >
> > Joel
> >
> > On Apr 2, 2012, at 2:46 AM, Silviu Baranga wrote:
> >
> > > Hi Joel,
> > >
> > > I've modified the test to check that the instruction
> > > is undefined for ARM v4 and valid for ARM v5TE.
> > >
> > > Regards,
> > > Silviu
> > >
> > > On Mar 30, 2012, at 19:11, Joel Jones wrote:
> > >>
> > >> Silviu:
> > >>
> > >> Should there be a CHECK-NOT to test that 0xd0000001
> > >> isn't decoded as ldrsb or a CHECK that it comes out undefined?
> > >>
> > >> Of course, if this is dependent upon which ARM variant as to
> > >> whether it is undefined or not, then you might want >1 variant of
> > >> this test with variant RUN lines.
> > >>
> > >> Joel
> > >>
> > >> On Mar 30, 2012, at 10:47 AM, Silviu Baranga wrote:
> > >>
> > >>> Hi,
> > >>>
> > >>> I've modified the patch to add a regression test
> > >>> for this.
> > >>>
> > >>> Because the break statement is missing, the ARM
> > >>> ldrd instruction 0xd0000001 is decoded to a ldrsb
> > >>> instruction instead of being undefined for
> > >>> ARMv4. The 20th bit should be 1 for the
> > >>> ldrsb instruction, which is not the case here.
> > >>>
> > >>> Cheers,
> > >>> Silviu
> > >>>
> > >>>> -----Original Message-----
> > >>>> From: David Blaikie [mailto:dblaikie at gmail.com]
> > >>>> Sent: 30 March 2012 16:26
> > >>>> To: Silviu Baranga
> > >>>> Cc: llvm-commits at cs.uiuc.edu
> > >>>> Subject: Re: [llvm-commits] [patch]Fix for TableGen decoder
> > >> generator
> > >>>>
> > >>>> On Fri, Mar 30, 2012 at 2:04 AM, Silviu Baranga
> <silbar01 at arm.com>
> > >>>> wrote:
> > >>>>> Hi,
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>> TableGen's decoder generator does not add a break in the switch
> > >>>> statements
> > >>>>> for decoding structure's leaf nodes, because it considers that
> > the
> > >>>> leaf
> > >>>>> nodes will always exit with a return. This is however not true
> > for
> > >>>> some
> > >>>>> backends (for example the ARM backend) where we have to match
> > >>>> multiple
> > >>>>> architectures and an 'if' statement is generated to guard the
> > leaf
> > >>>> node.
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>> When failing the architecture check, without the break
> statement,
> > >> the
> > >>>>> decoder will incorrectly fall through to the next branch and
> > match
> > >>>> other
> > >>>>> instructions that do  not correspond to the input bitpattern.
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>> The attached patch fixes this by making TableGen always emit a
> > >> break
> > >>>>> statement for leaf nodes.
> > >>>>
> > >>>> Do you have a test case for the bug that exposed this?
> > >>>>
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>> Please review this patch.
> > >>>>>
> > >>>>>
> > >>>>>
> > >>>>> Thanks,
> > >>>>>
> > >>>>> Silviu
> > >>>>>
> > >>>>>
> > >>>>> _______________________________________________
> > >>>>> llvm-commits mailing list
> > >>>>> llvm-commits at cs.uiuc.edu
> > >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > >>>>>
> > >>> <tblgen.diff>_______________________________________________
> > >>> llvm-commits mailing list
> > >>> llvm-commits at cs.uiuc.edu
> > >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > >>
> > >>
> > > <tblgen.diff>
> >
> >