[llvm-commits] [llvm] r153766 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vswp.s

[Jim Grosbach]

Author: grosbach
Date: Fri Mar 30 13:53:01 2012
New Revision: 153766

URL: http://llvm.org/viewvc/llvm-project?rev=153766&view=rev
Log:
ARM encoding for VSWP got the second operand incorrect.

Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

Added:
    llvm/trunk/test/MC/ARM/neon-vswp.s
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=153766&r1=153765&r2=153766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Mar 30 13:53:01 2012
@@ -4787,12 +4787,12 @@
 
 // Vector Swap
 def  VSWPd    : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
-                     (outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1),
-                     NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
+                     (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
+                     NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
                      []>;
 def  VSWPq    : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
-                     (outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1),
-                     NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
+                     (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
+                     NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
                      []>;
 
 // Vector Move Operations.

Added: llvm/trunk/test/MC/ARM/neon-vswp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vswp.s?rev=153766&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vswp.s (added)
+++ llvm/trunk/test/MC/ARM/neon-vswp.s Fri Mar 30 13:53:01 2012
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
+
+vswp d1, d2
+vswp q1, q2
+
+@ CHECK: vswp	d1, d2                  @ encoding: [0x02,0x10,0xb2,0xf3]
+@ CHECK: vswp	q1, q2                  @ encoding: [0x44,0x20,0xb2,0xf3]