[llvm-commits] [patch]Fix for TableGen decoder generator
silbar01 at arm.com
Fri Mar 30 10:47:14 PDT 2012
I've modified the patch to add a regression test
Because the break statement is missing, the ARM
ldrd instruction 0xd0000001 is decoded to a ldrsb
instruction instead of being undefined for
ARMv4. The 20th bit should be 1 for the
ldrsb instruction, which is not the case here.
> -----Original Message-----
> From: David Blaikie [mailto:dblaikie at gmail.com]
> Sent: 30 March 2012 16:26
> To: Silviu Baranga
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [patch]Fix for TableGen decoder generator
> On Fri, Mar 30, 2012 at 2:04 AM, Silviu Baranga <silbar01 at arm.com>
> > Hi,
> > TableGen's decoder generator does not add a break in the switch
> > for decoding structure's leaf nodes, because it considers that the
> > nodes will always exit with a return. This is however not true for
> > backends (for example the ARM backend) where we have to match
> > architectures and an 'if' statement is generated to guard the leaf
> > When failing the architecture check, without the break statement, the
> > decoder will incorrectly fall through to the next branch and match
> > instructions that do not correspond to the input bitpattern.
> > The attached patch fixes this by making TableGen always emit a break
> > statement for leaf nodes.
> Do you have a test case for the bug that exposed this?
> > Please review this patch.
> > Thanks,
> > Silviu
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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