[llvm-commits] Request for Review - avoid register pressure with read/modify/write instructions

[Evan Cheng]

The store fusing case should be handled by the tablegen generated code. This is a special case because generated code can't handle load / op / store fusion when the operation produces a flag.

Evan

On Mar 28, 2012, at 6:15 PM, Joerg Sonnenberger wrote:

> On Wed, Mar 28, 2012 at 11:12:49AM -0700, Joel Jones wrote:
>> This is a code change to add support for changing instruction sequences of the form:
>> 
>>  load
>>  inc/dec of 8/16/32/64 bits
>>  store
>> 
>> into the appropriate X86 inc/dec through memory instruction:
>> 
>>  inc[qlwb] / dec[qlwb]
> 
> At the moment you reject the transformation if anything else uses the
> load. Wouldn't it still make sense to fuse the inc/dec with the store,
> if the operand is not volatile? Or does that violate the memory model?
> 
> Joerg
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