[llvm-commits] [llvm] r153163 - /llvm/trunk/test/CodeGen/Generic/misched.ll

[Andrew Trick]

Author: atrick
Date: Tue Mar 20 23:12:19 2012
New Revision: 153163

URL: http://llvm.org/viewvc/llvm-project?rev=153163&view=rev
Log:
misched: beginning to add unit tests

Added:
    llvm/trunk/test/CodeGen/Generic/misched.ll

Added: llvm/trunk/test/CodeGen/Generic/misched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/misched.ll?rev=153163&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/misched.ll (added)
+++ llvm/trunk/test/CodeGen/Generic/misched.ll Tue Mar 20 23:12:19 2012
@@ -0,0 +1,20 @@
+; RUN: llc -enable-misched -misched=shuffle -misched-bottomup < %s
+; XFAIL: *
+;
+; Interesting MachineScheduler cases.
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+
+; From oggenc.
+; After coalescing, we have a dead superreg (RAX) definition.
+define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
+entry:
+  br i1 undef, label %for.cond.preheader, label %if.end
+
+for.cond.preheader:                               ; preds = %entry
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind
+  unreachable
+
+if.end:                                           ; preds = %entry
+  ret void
+}