[llvm-commits] [PATCH] Fix for some unpredictable instructions on ARM

[Silviu Baranga]

Commited in r153250 (mul.diff), r153251 (ldr.diff) and r153252
(addrmode3.diff).

 

Regards,

Silviu

 

From: Owen Anderson [mailto:owen at apple.com] 
Sent: 21 March 2012 23:14
To: Jim Grosbach
Cc: Silviu Baranga; Owen Anderson; llvm-commits at cs.uiuc.edu LLVM
Subject: Re: [PATCH] Fix for some unpredictable instructions on ARM

 

Looks fine, other than a bit of trailing whitespace. ;-)

 

--Owen

 

On Mar 21, 2012, at 3:56 PM, Jim Grosbach <grosbach at apple.com> wrote:





This all seems reasonable to me. Owen, what do you think?

 

-Jim

 

On Mar 21, 2012, at 3:47 AM, Silviu Baranga <silbar01 at arm.com> wrote:





Hi,

 

The ARM instructions:

    STRD, STRH, LDRD, LDRH, LDRSH, LDRSB, LDRSBT, LDRHT, LDRSHT, MUL

have some corner cases in which are unpredictable. In these cases the
disassembler should

still disassemble the instructions instead of rejecting them.

The attached standalone patches fix this.

  

 - addrmode3.diff - STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions.
The patch

                  modifies the C++ ARM disassembler code to add the checking
conditions, which are

                  too complex to introduce with tablegen files.

 - ldr.diff - LDRSBT, LDRHT and LDRSHT  instructions. The patch introduces a
decoder

                 method because of the Rn == Rt unpredictability condition
that is common to

                 all the instructions above.

- mul.diff -  MUL instruction. The patch changes the TableGen description of
the MUL

                 Instruction in order to reflect the fact that the
instruction is unpredictable when

                either of the Rd, Rn or Rm register operands are the pc
register.

 

All patches add regression tests for the modifications.

 

Please review.

 

Thanks,

Silviu

<addrmode3.diff><ldr.diff><mul.diff>

 

 
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