[llvm-commits] [llvm] r152824 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll test/CodeGen/ARM/2010-12-07-PEIBug.ll
Lang Hames
lhames at gmail.com
Thu Mar 15 11:49:02 PDT 2012
Author: lhames
Date: Thu Mar 15 13:49:02 2012
New Revision: 152824
URL: http://llvm.org/viewvc/llvm-project?rev=152824&view=rev
Log:
Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=152824&r1=152823&r2=152824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Mar 15 13:49:02 2012
@@ -456,6 +456,8 @@
setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
}
+ setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
+
if (Subtarget->hasNEON()) {
addDRTypeForNEON(MVT::v2f32);
addDRTypeForNEON(MVT::v8i8);
@@ -3673,6 +3675,27 @@
return Result;
}
+SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) const {
+ if (!ST->useNEONForSinglePrecisionFP() || !ST->hasVFP3() || ST->hasD16())
+ return SDValue();
+
+ ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
+ assert(Op.getValueType() == MVT::f32 &&
+ "ConstantFP custom lowering should only occur for f32.");
+
+ APFloat FPVal = CFP->getValueAPF();
+ int ImmVal = ARM_AM::getFP32Imm(FPVal);
+ if (ImmVal == -1)
+ return SDValue();
+
+ DebugLoc DL = Op.getDebugLoc();
+ SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
+ SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32, NewVal);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
+ DAG.getConstant(0, MVT::i32));
+}
+
/// isNEONModifiedImm - Check if the specified splat value corresponds to a
/// valid vector constant for a NEON instruction with a "modified immediate"
/// operand (e.g., VMOV). If so, return the encoded value.
@@ -5109,6 +5132,7 @@
case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
case ISD::SETCC: return LowerVSETCC(Op, DAG);
+ case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=152824&r1=152823&r2=152824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Mar 15 13:49:02 2012
@@ -434,6 +434,8 @@
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) const;
Modified: llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll?rev=152824&r1=152823&r2=152824&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll Thu Mar 15 13:49:02 2012
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+; RUN: llc -mcpu=cortex-a8 -mattr=-neonfp < %s | FileCheck %s
; PR5423
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll?rev=152824&r1=152823&r2=152824&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-07-PEIBug.ll Thu Mar 15 13:49:02 2012
@@ -4,36 +4,12 @@
define hidden void @foo() nounwind ssp {
entry:
; CHECK: foo:
-; CHECK: push {r7, lr}
-; CHECK-NEXT: mov r7, sp
+; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vpush {d10, d11}
- %tmp40 = load <4 x i8>* undef
- %tmp41 = extractelement <4 x i8> %tmp40, i32 2
- %conv42 = zext i8 %tmp41 to i32
- %conv43 = sitofp i32 %conv42 to float
- %div44 = fdiv float %conv43, 2.560000e+02
- %vecinit45 = insertelement <4 x float> undef, float %div44, i32 2
- %vecinit46 = insertelement <4 x float> %vecinit45, float 1.000000e+00, i32 3
- store <4 x float> %vecinit46, <4 x float>* undef
- br i1 undef, label %if.then105, label %if.else109
-
-if.then105: ; preds = %entry
- br label %if.end114
-
-if.else109: ; preds = %entry
- br label %if.end114
-
-if.end114: ; preds = %if.else109, %if.then105
- %call185 = call float @bar()
- %vecinit186 = insertelement <4 x float> undef, float %call185, i32 1
- %call189 = call float @bar()
- %vecinit190 = insertelement <4 x float> %vecinit186, float %call189, i32 2
- %vecinit191 = insertelement <4 x float> %vecinit190, float 1.000000e+00, i32 3
- store <4 x float> %vecinit191, <4 x float>* undef
+ tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind
; CHECK: vpop {d10, d11}
; CHECK-NEXT: vpop {d8}
-; CHECK-NEXT: pop {r7, pc}
ret void
}
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