[llvm-commits] [llvm] r150365 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td
Demikhovsky, Elena
elena.demikhovsky at intel.com
Thu Mar 15 00:47:01 PDT 2012
This release breaks conformance tests.
Debug+Asserts/bin/llc -mattr=+avx test.ll
LLVM ERROR: Cannot select: 0x1d418b0: v8f32 = vector_shuffle 0x1d41ab0, 0x1d41bb0<8,1,2,3,4,5,6,7> [ID=14]
0x1d41ab0: v8f32 = BUILD_VECTOR 0x1d416b0, 0x1d416b0, 0x1d416b0, 0x1d416b0, 0x1d416b0, 0x1d416b0, 0x1d416b0, 0x1d416b0 [ID=11]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d416b0: f32 = TargetConstantFP<0.000000e+00> [ID=2]
0x1d41bb0: v8f32 = insert_subvector 0x1d419b0, 0x1d41eb0, 0x1d415b0 [ID=13]
0x1d419b0: v8f32 = undef [ID=3]
0x1d41eb0: v4f32 = vector_shuffle 0x1d412b0, 0x1d417b0<2,u,u,u> [ID=12]
0x1d412b0: v4f32,ch = load 0x1d199d0, 0x1d411b0, 0x1d411b0<LD16[undef]> [ID=10]
0x1d411b0: i64 = undef [ORD=1] [ID=1]
0x1d411b0: i64 = undef [ORD=1] [ID=1]
0x1d417b0: v4f32 = undef [ID=4]
0x1d415b0: i32 = Constant<0> [ID=5]
- Elena
-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper
Sent: Monday, February 13, 2012 09:24
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [llvm] r150365 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td
Author: ctopper
Date: Mon Feb 13 01:23:41 2012
New Revision: 150365
URL: http://llvm.org/viewvc/llvm-project?rev=150365&view=rev
Log:
Still more vector_shuffle pattern removal.
Modified:
llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=150365&r1=150364&r2=150365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Feb 13 01:23:41 2012
@@ -385,16 +385,6 @@
return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
}]>;
-def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
- (vector_shuffle node:$lhs, node:$rhs), [{
- return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
-}]>;
-
-def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
- (vector_shuffle node:$lhs, node:$rhs), [{
- return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
-}]>;
-
def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
(extract_subvector node:$bigvec,
node:$index), [{
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=150365&r1=150364&r2=150365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Feb 13 01:23:41 2012
@@ -1192,24 +1192,24 @@
def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract
- (unpckh (bc_v2f64 (v4f32 VR128:$src)),
- (undef)), (iPTR 0))), addr:$dst)]>,
- VEX;
+ (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
+ (bc_v2f64 (v4f32 VR128:$src))),
+ (iPTR 0))), addr:$dst)]>, VEX;
def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract
- (v2f64 (unpckh VR128:$src, (undef))),
- (iPTR 0))), addr:$dst)]>,
- VEX;
+ (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
+ (iPTR 0))), addr:$dst)]>, VEX;
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract
- (unpckh (bc_v2f64 (v4f32 VR128:$src)),
- (undef)), (iPTR 0))), addr:$dst)]>;
+ (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
+ (bc_v2f64 (v4f32 VR128:$src))),
+ (iPTR 0))), addr:$dst)]>;
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract
- (v2f64 (unpckh VR128:$src, (undef))),
+ (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
(iPTR 0))), addr:$dst)]>;
let Predicates = [HasAVX] in {
@@ -1238,15 +1238,6 @@
def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))),
(VMOVHPDrm VR128:$src1, addr:$src2)>;
-
- // Store patterns
- def : Pat<(store (f64 (vector_extract
- (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
- (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
- (VMOVHPSmr addr:$dst, VR128:$src)>;
- def : Pat<(store (f64 (vector_extract
- (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
- (VMOVHPDmr addr:$dst, VR128:$src)>;
}
let Predicates = [HasSSE1] in {
@@ -1262,12 +1253,6 @@
def : Pat<(X86Movlhps VR128:$src1,
(bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
(MOVHPSrm VR128:$src1, addr:$src2)>;
-
- // Store patterns
- def : Pat<(store (f64 (vector_extract
- (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
- (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
- (MOVHPSmr addr:$dst, VR128:$src)>;
}
let Predicates = [HasSSE2] in {
@@ -1283,11 +1268,6 @@
def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))),
(MOVHPDrm VR128:$src1, addr:$src2)>;
-
- // Store patterns
- def : Pat<(store (f64 (vector_extract
- (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
- (MOVHPDmr addr:$dst, VR128:$src)>;
}
//===----------------------------------------------------------------------===//
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