[llvm-commits] [llvm] r151571 - in /llvm/trunk: include/llvm/MC/MCAsmBackend.h lib/MC/MCAssembler.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/ARM/MCTargetDesc/ARMEL
Jan Voung
jvoung at google.com
Mon Mar 12 17:32:32 PDT 2012
Hi Jim,
How does "fixup_arm_bl" differ from the "fixup_arm_condbranch" that was
introduced in http://llvm.org/viewvc/llvm-project?view=rev&revision=124895?
For the change to ARMELFObjectWriter.cpp, we still need conditional bl
instructions to have R_ARM_JUMP24 relocs (which fixup_arm_condbranch helped
do), instead of R_ARM_CALL.
- Jan
On Mon, Feb 27, 2012 at 1:36 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Mon Feb 27 15:36:23 2012
> New Revision: 151571
>
> URL: http://llvm.org/viewvc/llvm-project?rev=151571&view=rev
> Log:
> ARM BL/BLX instruction fixups should use relocations.
>
> We on the linker to resolve calls to the appropriate BL/BLX instruction
> to make interworking function correctly. It uses the symbol in the
> relocation to do that, so we need to be careful about being too clever.
>
> To enable this for ARM mode, split the BL/BLX fixup kind off from the
> unconditional-branch fixups.
>
> rdar://10927209
>
> Modified:
> llvm/trunk/include/llvm/MC/MCAsmBackend.h
> llvm/trunk/lib/MC/MCAssembler.cpp
> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> llvm/trunk/test/MC/ARM/arm_fixups.s
> llvm/trunk/test/MC/ARM/basic-arm-instructions.s
>
> Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCAsmBackend.h (original)
> +++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Mon Feb 27 15:36:23 2012
> @@ -92,11 +92,13 @@
> virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
>
> /// processFixupValue - Target hook to adjust the literal value of a
> fixup
> - /// if necessary. The default does nothing.
> + /// if necessary. IsResolved signals whether the caller believes a
> relocation
> + /// is needed; the target can modify the value. The default does
> nothing.
> virtual void processFixupValue(const MCAssembler &Asm,
> const MCAsmLayout &Layout,
> const MCFixup &Fixup, const MCFragment
> *DF,
> - MCValue &Target, uint64_t &Value) {}
> + MCValue &Target, uint64_t &Value,
> + bool &IsResolved) {}
>
> /// @}
>
>
> Modified: llvm/trunk/lib/MC/MCAssembler.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAssembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Feb 27 15:36:23 2012
> @@ -299,8 +299,10 @@
> Value -= Offset;
> }
>
> - // Let the backend adjust the fixup value if necessary.
> - Backend.processFixupValue(*this, Layout, Fixup, DF, Target, Value);
> + // Let the backend adjust the fixup value if necessary, including
> whether
> + // we need a relocation.
> + Backend.processFixupValue(*this, Layout, Fixup, DF, Target, Value,
> + IsResolved);
>
> return IsResolved;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Feb 27 15:36:23 2012
> @@ -189,6 +189,8 @@
> unsigned Op) const { return 0; }
> unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
> const { return 0; }
> + unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
> + const { return 0; }
> unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
> const { return 0; }
> unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Feb 27 15:36:23 2012
> @@ -349,13 +349,11 @@
> // Call target for ARM. Handles conditional/unconditional
> // FIXME: rename bl_target to t2_bltarget?
> def bl_target : Operand<i32> {
> - // Encoded the same as branch targets.
> - let EncoderMethod = "getARMBranchTargetOpValue";
> + let EncoderMethod = "getARMBLTargetOpValue";
> let OperandType = "OPERAND_PCREL";
> }
>
> def blx_target : Operand<i32> {
> - // Encoded the same as branch targets.
> let EncoderMethod = "getARMBLXTargetOpValue";
> let OperandType = "OPERAND_PCREL";
> }
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Feb 27
> 15:36:23 2012
> @@ -78,6 +78,8 @@
> { "fixup_t2_condbranch", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_t2_uncondbranch", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_thumb_br", 0, 16,
> MCFixupKindInfo::FKF_IsPCRel },
> +{ "fixup_arm_bl", 0, 24,
> MCFixupKindInfo::FKF_IsPCRel },
> +{ "fixup_arm_blx", 0, 24,
> MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_thumb_bl", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_thumb_blx", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_thumb_cb", 0, 16,
> MCFixupKindInfo::FKF_IsPCRel },
> @@ -106,18 +108,28 @@
> /// if necessary.
> void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
> const MCFixup &Fixup, const MCFragment *DF,
> - MCValue &Target, uint64_t &Value) {
> + MCValue &Target, uint64_t &Value,
> + bool &IsResolved) {
> + const MCSymbolRefExpr *A = Target.getSymA();
> // Some fixups to thumb function symbols need the low bit (thumb bit)
> // twiddled.
> if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
> (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
> (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
> - if (const MCSymbolRefExpr *A = Target.getSymA()) {
> + if (A) {
> const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
> if (Asm.isThumbFunc(&Sym))
> Value |= 1;
> }
> }
> + // We must always generate a relocation for BL/BLX instructions if we
> have
> + // a symbol to reference, as the linker relies on knowing the
> destination
> + // symbol's thumb-ness to get interworking right.
> + if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
> + (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
> + (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
> + (unsigned)Fixup.getKind() == ARM::fixup_arm_bl))
> + IsResolved = false;
> }
>
> bool mayNeedRelaxation(const MCInst &Inst) const;
> @@ -343,6 +355,8 @@
>
> case ARM::fixup_arm_condbranch:
> case ARM::fixup_arm_uncondbranch:
> + case ARM::fixup_arm_bl:
> + case ARM::fixup_arm_blx:
> // These values don't encode the low two bits since they're always
> zero.
> // Offset by 8 just as above.
> return 0xffffff & ((Value - 8) >> 2);
> @@ -552,6 +566,8 @@
> case ARM::fixup_arm_ldst_pcrel_12:
> case ARM::fixup_arm_pcrel_10:
> case ARM::fixup_arm_adr_pcrel_12:
> + case ARM::fixup_arm_bl:
> + case ARM::fixup_arm_blx:
> case ARM::fixup_arm_condbranch:
> case ARM::fixup_arm_uncondbranch:
> return 3;
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Mon Feb
> 27 15:36:23 2012
> @@ -177,6 +177,8 @@
> break;
> }
> break;
> + case ARM::fixup_arm_bl:
> + case ARM::fixup_arm_blx:
> case ARM::fixup_arm_uncondbranch:
> switch (Modifier) {
> case MCSymbolRefExpr::VK_ARM_PLT:
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h Mon Feb 27
> 15:36:23 2012
> @@ -59,6 +59,12 @@
> // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
> fixup_arm_thumb_br,
>
> + // fixup_arm_bl - Fixup for ARM BL instructions.
> + fixup_arm_bl,
> +
> + // fixup_arm_blx - Fixup for ARM BLX instructions.
> + fixup_arm_blx,
> +
> // fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
> fixup_arm_thumb_bl,
>
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Mon Feb 27
> 15:36:23 2012
> @@ -118,8 +118,10 @@
> /// branch target.
> uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups)
> const;
> + uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
> + SmallVectorImpl<MCFixup> &Fixups) const;
> uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
> - SmallVectorImpl<MCFixup> &Fixups)
> const;
> + SmallVectorImpl<MCFixup> &Fixups) const;
>
> /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
> /// ADR label target.
> @@ -592,16 +594,21 @@
> }
>
> uint32_t ARMMCCodeEmitter::
> +getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
> + SmallVectorImpl<MCFixup> &Fixups) const {
> + const MCOperand MO = MI.getOperand(OpIdx);
> + if (MO.isExpr())
> + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_bl, Fixups);
> +
> + return MO.getImm() >> 2;
> +}
> +
> +uint32_t ARMMCCodeEmitter::
> getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const {
> const MCOperand MO = MI.getOperand(OpIdx);
> - if (MO.isExpr()) {
> - if (HasConditionalBranch(MI))
> - return ::getBranchTargetOpValue(MI, OpIdx,
> - ARM::fixup_arm_condbranch, Fixups);
> - return ::getBranchTargetOpValue(MI, OpIdx,
> - ARM::fixup_arm_uncondbranch, Fixups);
> - }
> + if (MO.isExpr())
> + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx,
> Fixups);
>
> return MO.getImm() >> 1;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Mon Feb
> 27 15:36:23 2012
> @@ -82,6 +82,8 @@
> case ARM::fixup_arm_adr_pcrel_12:
> case ARM::fixup_arm_condbranch:
> case ARM::fixup_arm_uncondbranch:
> + case ARM::fixup_arm_bl:
> + case ARM::fixup_arm_blx:
> RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
> // Report as 'long', even though that is not quite accurate.
> Log2Size = llvm::Log2_32(4);
>
> Modified: llvm/trunk/test/MC/ARM/arm_fixups.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/arm_fixups.s (original)
> +++ llvm/trunk/test/MC/ARM/arm_fixups.s Mon Feb 27 15:36:23 2012
> @@ -3,7 +3,7 @@
>
> bl _printf
> @ CHECK: bl _printf @ encoding: [A,A,A,0xeb]
> -@ CHECK: @ fixup A - offset: 0, value: _printf, kind:
> fixup_arm_uncondbranch
> +@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_bl
>
> mov r9, :lower16:(_foo)
> movw r9, :lower16:(_foo)
>
> Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=151571&r1=151570&r2=151571&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
> +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Feb 27 15:36:23
> 2012
> @@ -388,9 +388,9 @@
> blx #16212288
>
> @ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
> -@ CHECK: @ fixup A - offset: 0, value: _bar, kind:
> fixup_arm_uncondbranch
> +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_bl
> @ CHECK: blx _bar @ encoding: [A,A,A,0xfa]
> - @ fixup A - offset: 0, value: _bar, kind:
> fixup_arm_uncondbranch
> + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx
> @ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b]
> @ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa]
> @ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa]
>
>
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