[llvm-commits] [llvm] r152019 - in /llvm/trunk: include/llvm/MC/MCRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp

[Jakob Stoklund Olesen]

On Mar 5, 2012, at 5:09 PM, Craig Topper <craig.topper at gmail.com> wrote:

> How many register classes are the 16k targets using. Just curious because this change was to the size of register class IDs.

There is no good reason to shrink register class IDs to 8 bits.

You also shrank RegSetSize to 8 bits which limited physregs to 4k.

Shrinking RegSize and Alignment to 8 bits also doesn't make sense when x86 already has 32-byte registers.

Don't impose tight limits for diminutive gains. It's fine to limit the number of physregs to 64k, but that's it.

/jakob