[llvm-commits] [llvm] r151260 - in /llvm/trunk/test/CodeGen/ARM: debug-info-sreg2.ll fcopysign.ll

Jakob Stoklund Olesen stoklund at 2pi.dk
Thu Feb 23 09:19:35 PST 2012


Author: stoklund
Date: Thu Feb 23 11:19:34 2012
New Revision: 151260

URL: http://llvm.org/viewvc/llvm-project?rev=151260&view=rev
Log:
Make tests less sensitive to scheduling changes.

Modified:
    llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
    llvm/trunk/test/CodeGen/ARM/fcopysign.ll

Modified: llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll?rev=151260&r1=151259&r2=151260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll Thu Feb 23 11:19:34 2012
@@ -6,9 +6,9 @@
 ;CHECK: Ldebug_loc0:
 ;CHECK-NEXT:        .long   Ltmp0
 ;CHECK-NEXT:        .long   Ltmp1
-;CHECK-NEXT: Lset[[N:[0-9]+]] = Ltmp8-Ltmp7        @ Loc expr size
+;CHECK-NEXT: Lset[[N:[0-9]+]] = Ltmp{{[0-9]+}}-Ltmp[[M:[0-9]+]]        @ Loc expr size
 ;CHECK-NEXT:        .short  Lset[[N]]
-;CHECK-NEXT: Ltmp7:
+;CHECK-NEXT: Ltmp[[M]]:
 ;CHECK-NEXT:        .byte   144                     @ DW_OP_regx for S register
 
 define void @_Z3foov() optsize ssp {

Modified: llvm/trunk/test/CodeGen/ARM/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fcopysign.ll?rev=151260&r1=151259&r2=151260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fcopysign.ll Thu Feb 23 11:19:34 2012
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
-; RUN: llc < %s -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
+; RUN: llc < %s -disable-post-ra -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
+; RUN: llc < %s -disable-post-ra -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
 
 ; rdar://8984306
 define float @test1(float %x, float %y) nounwind {
@@ -60,8 +60,8 @@
 define float @test5() nounwind {
 entry:
 ; SOFT: test5:
-; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
 ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
+; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
 ; SOFT: vbsl [[REG6]], [[REG7]], 
   %0 = tail call double (...)* @bar() nounwind





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