[llvm-commits] [PATCH] Teach the MC about UNPREDICTABLE

[James Molloy]

Hi Owen,

Do you have any other comments about this patch or is it OK to commit?

Cheers,

James

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of James Molloy
Sent: 06 February 2012 19:15
To: Owen Anderson
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Teach the MC about UNPREDICTABLE

Hi Owen,

For the generated disassembler it only adds two lines of code and only on
instructions that require it. The difference in size before and after this
patch is +2 lines, because it is only hooked up to tBX.

There is no noticeable build time difference.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at mac.com]
Sent: 06 February 2012 18:19
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Teach the MC about UNPREDICTABLE

James,

I like the concept of this feature, and it'd be nice if it could help use
eliminate more of the hand-written decoding hooks.  However, I'm concerned
about the impact it will have on LLVM's build time.  Have you looked at how
much bigger this makes the generated disassembler file?  It already takes a
very long time to compile, and I'm wage to avoid making it any worse.

--Owen

On Feb 6, 2012, at 2:42 AM, James Molloy wrote:

Hi,

ARM has the concept of an "unpredictable" instruction - one which is valid
(and will be executed) but whose results are not defined. An example of an
unpredictable instruction is a load with address increment and writeback
where the writeback register is the same as the load destination.

The MC disassembler has the concept of a "soft failure" which maps well to
unpredictability (coincidentally because it was added for that purpose).
However this soft failure can currently only be triggered by manual C++ code
such as that in ARMDisassembler.cpp - it cannot be triggered from
tablegen-generated code.

The attached patch adds this functionality. It adds the ability for the
FixedLenDecoderEmitter to take into account a bitfield in a tablegen record
called "SoftFail" that mirrors the "Inst" field.

If a bitpattern BP matches the Inst field of an instruction record but
differs from Inst in any bits which are set to '1' in the SoftFail field,
then that instruction is matched by the disassembler but the status SoftFail
is returned instead of Success.

For example, this is a modified Thumb BX instruction with unpredictability
modelled as per the ARMARM:

def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
            T1Special<{1,1,0,?}> {
    // A6.2.3 & A8.6.25
    bits<4> Rm;
    let Inst{6-3} = Rm;
    let Inst{2-0} = 0b000;
    // Any of the bottom 3 bits set is unpredictable.
    let SoftFail{2-0} = 0b111;
  }

And this is the generated disassembler code (new code bolded):

if ((Bits & ARM::ModeThumb)) {
  if (insn & 0x7)
    S = MCDisassembler::SoftFail;
  MI.setOpcode(2662);
  tmp = fieldFromInstruction16(insn, 3, 4);
  if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return
MCDisassembler::Fail;
    return S; // tBXT
}

This results in the MC now correctly identifying such an instruction:

$ echo '0x01 0x47' | ./bin/llvm-mc -triple thumbv7 -disassemble
<stdin>:1:1: warning: potentially undefined instruction encoding
0x01 0x47
^
                bx           r0

The patch works by removing any bits that could SoftFail from the set of
possible disassembly island values, and emitting an extra test if required
in the generated disassembler. If no SoftFail bits are set, no extra code
will be emitted.

In the ARM tablegen files, this patch aliases SoftFail to "Unpredictable" so
it is more recognisable what it is doing in the ARM world.

Please review! It wires the new functionality up to "tBX" as a proof of
concept and testing codepath, and adds a regression test.

Cheers,

James
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