[llvm-commits] [llvm] r149646 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/DeadMachineInstructionElim.cpp lib/CodeGen/MachineInstr.cpp lib/CodeGen/MachineLICM.cpp lib/Target/X86/X86ISelLowering.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Thu Feb  2 17:52:57 2012
New Revision: 149646

URL: http://llvm.org/viewvc/llvm-project?rev=149646&view=rev
Log:
Require non-NULL register masks.

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineOperand.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/MachineLICM.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Thu Feb  2 17:52:57 2012
@@ -446,12 +446,11 @@
     assert(isRegMask() && "Wrong MachineOperand accessor");
     // See TargetRegisterInfo.h.
     assert(PhysReg < (1u << 30) && "Not a physical register");
-    return !Contents.RegMask ||
-           !(Contents.RegMask[PhysReg / 32] & (1u << PhysReg % 32));
+    return !(Contents.RegMask[PhysReg / 32] & (1u << PhysReg % 32));
   }
 
   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
-  /// operand.  A NULL pointer means that all registers are clobbered.
+  /// operand.
   const uint32_t *getRegMask() const {
     assert(isRegMask() && "Wrong MachineOperand accessor");
     return Contents.RegMask;
@@ -616,6 +615,7 @@
   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
   ///
   static MachineOperand CreateRegMask(const uint32_t *Mask) {
+    assert(Mask && "Missing register mask");
     MachineOperand Op(MachineOperand::MO_RegisterMask);
     Op.Contents.RegMask = Mask;
     return Op;

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Feb  2 17:52:57 2012
@@ -376,7 +376,10 @@
   ///
   /// Bits are numbered from the LSB, so the bit for physical register Reg can
   /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
-  /// NULL pointer is equivalent to an all-zero mask.
+  ///
+  /// A NULL pointer means that no register mask will be used, and call
+  /// instructions should use implicit-def operands to indicate call clobbered
+  /// registers.
   ///
   virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
     // The default mask clobbers everything.  All targets should override.

Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Thu Feb  2 17:52:57 2012
@@ -175,10 +175,7 @@
           }
         } else if (MO.isRegMask()) {
           // Register mask of preserved registers. All clobbers are dead.
-          if (const uint32_t *Mask = MO.getRegMask())
-            LivePhysRegs.clearBitsNotInMask(Mask);
-          else
-            LivePhysRegs.reset();
+          LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
           LivePhysRegs |= ReservedRegs;
         }
       }

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Feb  2 17:52:57 2012
@@ -327,7 +327,7 @@
     OS << '>';
     break;
   case MachineOperand::MO_RegisterMask:
-    OS << (getRegMask() ? "<regmask>" : "<regmask:null>");
+    OS << "<regmask>";
     break;
   case MachineOperand::MO_Metadata:
     OS << '<';

Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Feb  2 17:52:57 2012
@@ -417,10 +417,7 @@
     // We can't hoist an instruction defining a physreg that is clobbered in
     // the loop.
     if (MO.isRegMask()) {
-      if (const uint32_t *Mask = MO.getRegMask())
-        PhysRegClobbers.setBitsNotInMask(Mask);
-      else
-        PhysRegClobbers.set();
+      PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
       continue;
     }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=149646&r1=149645&r2=149646&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb  2 17:52:57 2012
@@ -2515,8 +2515,8 @@
   // registers.
   if (UseRegMask) {
     const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
-    const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
-    Ops.push_back(DAG.getRegisterMask(Mask));
+    if (const uint32_t *Mask = TRI->getCallPreservedMask(CallConv))
+      Ops.push_back(DAG.getRegisterMask(Mask));
   }
 
   if (InFlag.getNode())