[llvm-commits] Hexagon VLIW instruction scheduler framework patch for review

[Sergei Larin]

Andrew, 

 

  I would much rather check this version in now, and later work on the
migration. We have numerous outstanding patches we are trying to upstream to
Hexagon, and this one is blocking. since it touches both target independent
and Hexagon sides. I'll happily transform the scheduler later, but I must
unblock everyone else in the team now. Thank you for understanding.

 

Sergei

 

--

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.

 

From: Andrew Trick [mailto:atrick at apple.com] 
Sent: Wednesday, February 01, 2012 1:43 AM
To: Sergei Larin
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] Hexagon VLIW instruction scheduler framework
patch for review

 

On Jan 31, 2012, at 7:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:

 

From:  <mailto:llvm-commits-bounces at cs.uiuc.edu>
llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu]
On Behalf Of Sergei Larin
Sent: Friday, January 27, 2012 10:47 AM
To:  <mailto:llvm-commits at cs.uiuc.edu> llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] Hexagon VLIW instruction scheduler framework patch
for review

 

 

  Hello everybody,

 

    Attached is initial patch for a VLIW specific scheduler framework that
utilizes deterministic finite automaton (DFA) .

 

Several key points:

-          The scheduler is largely based on the existing framework, but
introduces several VLIW specific concepts. It could be classified as a top
down list scheduler, critical path first, with DFA used for parallel
resources modeling. It also models and tracks register pressure in the way
similar to the current RegPressure scheduler. It employs a slightly
different way to compute "cost" function for all SUs in AQ which allows for
somewhat easier balancing of multiple heuristic inputs. Current version does
_not_ generates bundles/packets (but models them internally). It could be
easily modified to do so, and it is our plan to make it a part of bundle
generation in the near future.

-          The scheduler is enabled for the Hexagon backend. Comparing to
any existing scheduler, for this VLIW target this code produces between 1.9%
slowdown and 11% speedup on our internal test suite. This test set comprised
from a variety of real world applications ranging from DSP specific
applications to SPEC. Some DSP kernels (when taken out of context) enjoy up
to 20% speedup when compared to the "default" scheduling mechanism
(RegPressure pre-RA + post RA). Main reason for this kind of corner case
behavior is long chains of independent memory accesses that are
conservatively serialized by the default scheduler (and there is no HW
scheduler to sort it out at the run time).

-          This patch is an initial submission with a bare minimum of
features, and more heuristics will be added to it later. We prefer to submit
it in stages to simplify review process and improve SW management.

-          Patch also contains minor updates to two Hexagon specific tests
in order to compensate for new order of instructions generated by the
Hexagon backend __with scheduler disabled__.

-          SVN revision 149130. LLVM verification test run for x86 platform
detects no additional failures.

 

  Comments and reviews are eagerly anticipated J

 

I'm in the process of reviewing this and also reworking the codegen pass
configuration to make it easier for targets to plugin scheduling/bundling
and other passes. Hopefully you'll see the results of both tomorrow.

 

This is probably fine to checkin in the short term, but you could instead
move directly to scheduling machineinstrs after coalescing. Then you can
actually work on using MachineBundles. Will it work for you to use the
SourceListDAGScheduler and run your scheduler/bundler in the
MachineScheduler pass? I think this migration will have to come either now
or later for you.

 

-Andy

 

 

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