[llvm-commits] Tuning LLVM Greedy Register Allocator to optimize for code size when targeting ARM Thumb 2 instruction set

[Zino Benaissa]

Yes Evan, which is why this heuristic is also on when -O3 is used.

 

There are more opportunity if we desire to pursue them (for -Os
specifically). E.g.,  Use callee-save register, do less coalescing, do less
re-materialization for large immediate, use flatter weight as Jacob
proposed.

 

This heuristic improves overall register allocator for Thumb 2  mode. 

 

Thanks, 

-Zino  

 

From: Evan Cheng [mailto:evan.cheng at apple.com] 
Sent: Tuesday, January 24, 2012 10:54 PM
To: Zino Benaissa
Cc: llvm-commits at cs.uiuc.edu; rajav at codeaurora.org
Subject: Re: [llvm-commits] Tuning LLVM Greedy Register Allocator to
optimize for code size when targeting ARM Thumb 2 instruction set

 

Can you confirm that this change is not predicated on OptimizeForSize and
it's not designed to trade off speed for code size? I'm pretty sure that's
what you mean but I want to be sure.

 

Thanks,

 

Evan

 

On Jan 23, 2012, at 5:11 PM, Zino Benaissa wrote:





Description:

This contribution extends LLVM greedy Register Allocator to optimize for
code size when LLVM compiler targets ARM Thumb 2 instruction set. This
heuristic favors assigning register R0 through R7 to operands used in
instruction that can be encoded in 16 bits (16-bit is allowed only if R0-7
are used). Operands that appear most frequently in a function (and in
instructions that qualify) get R0-7 register.

This heuristic is turned on by default and has impact on generated code only
if -mthumb compiler switch is used. To turn this heuristic off use
-disable-favor-r0-7 feature flag.

 

This patch modifies: 
1) The LLVM greedy register allocator located in LLVM/CodeGen directory: To
add the new code size heuristic.
2) The ARM-specific flies located in LLVM/Target/ARM directory: To add the
function that determines which instruction can be encoded in 16-bits and a
fix to enable the compiler to emit CMN instruction in 16-bits encoding. 
3) The LLVM test suite: fix test/CodeGen/Thumb2/thumb2-cmn.ll test.

 

Performance impact:

I focused on -Os and -mthumb  flags. But observed similar improvement  with
-O3 and -mthumb. Runtime measured on Qualcomm 8660.

Code size:

-          SPEC2000  benchmarks between 0 to 0.6% code size reduction (with
no noticeable regression).   

-          EEMBC benchmarks between 0 to  6% reduction (no noticeable
regression).  Automotive and Networking average about 1% code size reduction
and Consumer about 0.5%.

Runtime:

-          SPEC2000 between -1% and 6% speed up (Spec2k/ammp 6%)

-          EEMBC overall averages faster -1 to 5%.

Modified:

   test/CodeGen/Thumb2/thumb2-cmn.ll

   include/llvm/Target/TargetInstrInfo.h

   include/llvm/CodeGen/LiveInterval.h

   lib/Target/ARM/Thumb2SizeReduction.cpp

   lib/Target/ARM/ARMBaseInstrInfo.cpp

   lib/Target/ARM/ARMBaseInstrInfo.h

   lib/CodeGen/RegAllocGreedy.cpp

   lib/CodeGen/CalcSpillWeights.cpp

  

for details see RACodeSize.txt

 

Testing:

See ARMTestSuiteResult.txt and ARMSimple-Os-mthumb.txt

Note -O3 is also completed on X86 and ARM CPUs

<RACodeSize.txt><ARMTestSuiteResult.txt><ARMsimple-Os-mthumb.txt>___________
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