[llvm-commits] [llvm] r148108 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrInfo.cpp X86InstrSSE.td X86MCInstLower.cpp

[Craig Topper]

How does foldMemoryOpImpl work for those patterns that are using subreg?
Won't it only create a v4i32 constant pool entry?

On Fri, Jan 13, 2012 at 10:42 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

>
> On Jan 13, 2012, at 10:29 AM, Craig Topper wrote:
>
> > Well I didn't understand the FIXME comment about the JIT issue around
> the AVX_SET0PSY and AVX_SET0PDY. So I did it this way. If you can shed any
> light on that FIXME that would be great.
>
> The (non-MC) JIT requires encoding bits on any instruction that reaches
> the end of codegen. The ExpandPostRAPseudos pass avoids this problem by
> expanding pseudos before they reach the JIT. Such pseudos don't need
> encoding information.
>
> That's why V_SET0 can be marked as a proper pseudo-instruction:
>
> def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
>
> > What about the V_SET0 having VR128, do we need a separate one for VR256
> or is there some way to do this?
>
> You can use (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm).
>
> There are already patterns like that:
>
> // AVX has no support for 256-bit integer instructions, but since the
> 128-bit
> // VPXOR instruction writes zero to its upper part, it's safe build zeros.
> def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0),
> sub_xmm)>;
> def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
>          (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
>
> def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0),
> sub_xmm)>;
> def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
>          (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
>
> /jakob
>
>


-- 
~Craig
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