[llvm-commits] [llvm] r148108 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrInfo.cpp X86InstrSSE.td X86MCInstLower.cpp

[Jakob Stoklund Olesen]

On Jan 13, 2012, at 12:12 AM, Craig Topper wrote:

> Author: ctopper
> Date: Fri Jan 13 02:12:35 2012
> New Revision: 148108
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=148108&view=rev
> Log:
> Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.

Hi Craig,

Can't you handle this the same way as the V_SET0 instruction?

It shouldn't be necessary to have AVX_SET0PSY, AVX_SET0PDY, and AVX2_SET0. Just use one pseudo-instruction that gets lowered PostRA. ExeDepsFix never needs to see it. It can work on the xor instructions.

/jakob