[llvm-commits] VECTOR_SUFFLE in avx - fixed - Please review

[Craig Topper]

If that's true, we probably need to recanonicalize the shuffle if its the
LHS went to UNDEF, but there's still something in RHS. We should move the
RHS to LHS.

On Wed, Jan 11, 2012 at 2:32 PM, Rotem, Nadav <nadav.rotem at intel.com> wrote:

>  Craig, ****
>
> ** **
>
> It looks like some node (scalar_to_vector in our case) is legalized into
> an UNDEF and the result is replaced using "DAG.ReplaceAllUsesWith".  I
> don’t think that we can do much about it. Let's do what Duncan said.****
>
> ** **
>
> Nadav****
>
> ** **
>
> *From:* llvm-commits-bounces at cs.uiuc.edu [mailto:
> llvm-commits-bounces at cs.uiuc.edu] *On Behalf Of *Craig Topper
> *Sent:* Wednesday, January 11, 2012 19:58
> *To:* Duncan Sands
> *Cc:* llvm-commits at cs.uiuc.edu
> *Subject:* Re: [llvm-commits] VECTOR_SUFFLE in avx - fixed - Please review
> ****
>
> ** **
>
> r147525 added canonicalizing to DAGCombiner that should make shuffles of
> two undefs turn into an undef. Is that code not working correctly for this
> case?
>
> ****
>
> On Wed, Jan 11, 2012 at 3:55 AM, Duncan Sands <baldrick at free.fr> wrote:***
> *
>
> Hi Elena,****
>
>
> > Fixed a bug in VECTOR_SHUFFLE****
>
> > lc: X86ISelLowering.cpp:6480: llvm::SDValue
> llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue,
> llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op
> 1 of shuffle should not be undef"' failed.
>
> if V1 is undef but V2IsUndef is false then you can now fall through to the
> following code.  How about at restoring the assertion, but putting it after
> your test.  While there, maybe introduce V1IsUndef for neatness.
>
> Ciao, Duncan.
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> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits****
>
>
>
>
> --
> ~Craig****
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-- 
~Craig
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