[llvm-commits] X86SSELevel for AVX architecture

Craig Topper craig.topper at gmail.com
Sun Jan 1 11:06:31 PST 2012

This is similar to the fix for the prefetch instruction in r146163. I think
the fence instructions and clflush are similarly broken. I'll see if I can
find any others and I'll commit a fix.

On Sun, Jan 1, 2012 at 10:18 AM, Umansky, Victor
<victor.umansky at intel.com>wrote:

>  Hi Evan,
> I noticed that in X86Subtarget constructor you set ‘X86SSELevel’ member
> of the class as  ‘NoMMXSSE’ in the case when  HasAVX member is set to
> ‘true’.
> Effectively that invalidates SSE features for AVX architecture - because
> hasSSEn() accessors return ‘false’ when HasAVXn() is ‘true’.
> I wonder whether this is the behavior which you’d like to enforce – as
> conceptually AVX architecture complements SSE rather than replaces it
> completely.
> I noticed this problem after discovering that LLVM fails to lower
> “sse2.fence” intrinsic when generating a code for AVX architecture –
> because this intrinsic is conditioned on hasSSE2() being ‘true’.
> Is that case was somehow missed from regression testing, or there is
> another way to lower that intrinsic?
> I’d appreciate your clarifications.
> Best Regards,
>      Victor Umansky
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