[llvm-commits] [llvm] r147383 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsCodeEmitter.cpp MipsMCInstLower.cpp MipsRegisterInfo.cpp
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Dec 30 13:09:41 PST 2011
Author: bruno
Date: Fri Dec 30 15:09:41 2011
New Revision: 147383
URL: http://llvm.org/viewvc/llvm-project?rev=147383&view=rev
Log:
Cleanup Mips code and rename some variables. Patch by Jack Carter
Modified:
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=147383&r1=147382&r2=147383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Dec 30 15:09:41 2011
@@ -66,10 +66,10 @@
}
void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
-
if (MI->isDebugValue()) {
+ SmallString<128> Str;
+ raw_svector_ostream OS(Str);
+
PrintDebugValueComment(MI, OS);
return;
}
@@ -178,7 +178,7 @@
if (Mips::CPURegsRegisterClass->contains(Reg))
break;
- unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
+ unsigned RegNum = getMipsRegisterNumbering(Reg);
if (Mips::AFGR64RegisterClass->contains(Reg)) {
FPUBitmask |= (3 << RegNum);
CSFPRegsSize += AFGR64RegSize;
@@ -193,7 +193,7 @@
// Set CPU Bitmask.
for (; i != e; ++i) {
unsigned Reg = CSI[i].getReg();
- unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg);
+ unsigned RegNum = getMipsRegisterNumbering(Reg);
CPUBitmask |= (1 << RegNum);
}
Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=147383&r1=147382&r2=147383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Fri Dec 30 15:09:41 2011
@@ -216,7 +216,7 @@
unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const {
if (MO.isReg())
- return MipsRegisterInfo::getRegisterNumbering(MO.getReg());
+ return getMipsRegisterNumbering(MO.getReg());
else if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
else if (MO.isGlobal()) {
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=147383&r1=147382&r2=147383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Fri Dec 30 15:09:41 2011
@@ -213,102 +213,102 @@
SmallVector<MCInst,
4>& MCInsts) {
unsigned Opc = MI->getOpcode();
- MCInst instr1, instr2, instr3, move;
+ MCInst Instr1, Instr2, Instr3, Move;
- bool two_instructions = false;
+ bool TwoInstructions = false;
assert(MI->getNumOperands() == 3);
assert(MI->getOperand(0).isReg());
assert(MI->getOperand(1).isReg());
- MCOperand target = LowerOperand(MI->getOperand(0));
- MCOperand base = LowerOperand(MI->getOperand(1));
- MCOperand atReg = MCOperand::CreateReg(Mips::AT);
- MCOperand zeroReg = MCOperand::CreateReg(Mips::ZERO);
-
- MachineOperand unloweredName = MI->getOperand(2);
- MCOperand name = LowerOperand(unloweredName);
-
- move.setOpcode(Mips::ADDu);
- move.addOperand(target);
- move.addOperand(atReg);
- move.addOperand(zeroReg);
+ MCOperand Target = LowerOperand(MI->getOperand(0));
+ MCOperand Base = LowerOperand(MI->getOperand(1));
+ MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
+ MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
+
+ MachineOperand UnLoweredName = MI->getOperand(2);
+ MCOperand Name = LowerOperand(UnLoweredName);
+
+ Move.setOpcode(Mips::ADDu);
+ Move.addOperand(Target);
+ Move.addOperand(ATReg);
+ Move.addOperand(ZeroReg);
switch (Opc) {
case Mips::ULW: {
// FIXME: only works for little endian right now
- MCOperand adj_name = LowerOperand(unloweredName, 3);
- if (base.getReg() == (target.getReg())) {
- instr1.setOpcode(Mips::LWL);
- instr1.addOperand(atReg);
- instr1.addOperand(base);
- instr1.addOperand(adj_name);
- instr2.setOpcode(Mips::LWR);
- instr2.addOperand(atReg);
- instr2.addOperand(base);
- instr2.addOperand(name);
- instr3 = move;
+ MCOperand AdjName = LowerOperand(UnLoweredName, 3);
+ if (Base.getReg() == (Target.getReg())) {
+ Instr1.setOpcode(Mips::LWL);
+ Instr1.addOperand(ATReg);
+ Instr1.addOperand(Base);
+ Instr1.addOperand(AdjName);
+ Instr2.setOpcode(Mips::LWR);
+ Instr2.addOperand(ATReg);
+ Instr2.addOperand(Base);
+ Instr2.addOperand(Name);
+ Instr3 = Move;
} else {
- two_instructions = true;
- instr1.setOpcode(Mips::LWL);
- instr1.addOperand(target);
- instr1.addOperand(base);
- instr1.addOperand(adj_name);
- instr2.setOpcode(Mips::LWR);
- instr2.addOperand(target);
- instr2.addOperand(base);
- instr2.addOperand(name);
+ TwoInstructions = true;
+ Instr1.setOpcode(Mips::LWL);
+ Instr1.addOperand(Target);
+ Instr1.addOperand(Base);
+ Instr1.addOperand(AdjName);
+ Instr2.setOpcode(Mips::LWR);
+ Instr2.addOperand(Target);
+ Instr2.addOperand(Base);
+ Instr2.addOperand(Name);
}
break;
}
case Mips::ULHu: {
// FIXME: only works for little endian right now
- MCOperand adj_name = LowerOperand(unloweredName, 1);
- instr1.setOpcode(Mips::LBu);
- instr1.addOperand(atReg);
- instr1.addOperand(base);
- instr1.addOperand(adj_name);
- instr2.setOpcode(Mips::LBu);
- instr2.addOperand(target);
- instr2.addOperand(base);
- instr2.addOperand(name);
- instr3.setOpcode(Mips::INS);
- instr3.addOperand(target);
- instr3.addOperand(atReg);
- instr3.addOperand(MCOperand::CreateImm(0x8));
- instr3.addOperand(MCOperand::CreateImm(0x18));
+ MCOperand AdjName = LowerOperand(UnLoweredName, 1);
+ Instr1.setOpcode(Mips::LBu);
+ Instr1.addOperand(ATReg);
+ Instr1.addOperand(Base);
+ Instr1.addOperand(AdjName);
+ Instr2.setOpcode(Mips::LBu);
+ Instr2.addOperand(Target);
+ Instr2.addOperand(Base);
+ Instr2.addOperand(Name);
+ Instr3.setOpcode(Mips::INS);
+ Instr3.addOperand(Target);
+ Instr3.addOperand(ATReg);
+ Instr3.addOperand(MCOperand::CreateImm(0x8));
+ Instr3.addOperand(MCOperand::CreateImm(0x18));
break;
}
case Mips::USW: {
// FIXME: only works for little endian right now
- assert (base.getReg() != target.getReg());
- two_instructions = true;
- MCOperand adj_name = LowerOperand(unloweredName, 3);
- instr1.setOpcode(Mips::SWL);
- instr1.addOperand(target);
- instr1.addOperand(base);
- instr1.addOperand(adj_name);
- instr2.setOpcode(Mips::SWR);
- instr2.addOperand(target);
- instr2.addOperand(base);
- instr2.addOperand(name);
+ assert (Base.getReg() != Target.getReg());
+ TwoInstructions = true;
+ MCOperand AdjName = LowerOperand(UnLoweredName, 3);
+ Instr1.setOpcode(Mips::SWL);
+ Instr1.addOperand(Target);
+ Instr1.addOperand(Base);
+ Instr1.addOperand(AdjName);
+ Instr2.setOpcode(Mips::SWR);
+ Instr2.addOperand(Target);
+ Instr2.addOperand(Base);
+ Instr2.addOperand(Name);
break;
}
case Mips::USH: {
- MCOperand adj_name = LowerOperand(unloweredName, 1);
- instr1.setOpcode(Mips::SB);
- instr1.addOperand(target);
- instr1.addOperand(base);
- instr1.addOperand(name);
- instr2.setOpcode(Mips::SRL);
- instr2.addOperand(atReg);
- instr2.addOperand(target);
- instr2.addOperand(MCOperand::CreateImm(8));
- instr3.setOpcode(Mips::SB);
- instr3.addOperand(atReg);
- instr3.addOperand(base);
- instr3.addOperand(adj_name);
+ MCOperand AdjName = LowerOperand(UnLoweredName, 1);
+ Instr1.setOpcode(Mips::SB);
+ Instr1.addOperand(Target);
+ Instr1.addOperand(Base);
+ Instr1.addOperand(Name);
+ Instr2.setOpcode(Mips::SRL);
+ Instr2.addOperand(ATReg);
+ Instr2.addOperand(Target);
+ Instr2.addOperand(MCOperand::CreateImm(8));
+ Instr3.setOpcode(Mips::SB);
+ Instr3.addOperand(ATReg);
+ Instr3.addOperand(Base);
+ Instr3.addOperand(AdjName);
break;
}
default:
@@ -316,8 +316,8 @@
assert(0 && "unaligned instruction not processed");
}
- MCInsts.push_back(instr1);
- MCInsts.push_back(instr2);
- if (!two_instructions) MCInsts.push_back(instr3);
+ MCInsts.push_back(Instr1);
+ MCInsts.push_back(Instr2);
+ if (!TwoInstructions) MCInsts.push_back(Instr3);
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=147383&r1=147382&r2=147383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Fri Dec 30 15:09:41 2011
@@ -45,98 +45,6 @@
const TargetInstrInfo &tii)
: MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
-/// getRegisterNumbering - Given the enum value for some register, e.g.
-/// Mips::RA, return the number that it corresponds to (e.g. 31).
-unsigned MipsRegisterInfo::
-getRegisterNumbering(unsigned RegEnum)
-{
- switch (RegEnum) {
- case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
- case Mips::D0:
- return 0;
- case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
- return 1;
- case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
- case Mips::D1:
- return 2;
- case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
- return 3;
- case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
- case Mips::D2:
- return 4;
- case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
- return 5;
- case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
- case Mips::D3:
- return 6;
- case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
- return 7;
- case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
- case Mips::D4:
- return 8;
- case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
- return 9;
- case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
- case Mips::D5:
- return 10;
- case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
- return 11;
- case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
- case Mips::D6:
- return 12;
- case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
- return 13;
- case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
- case Mips::D7:
- return 14;
- case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
- return 15;
- case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
- case Mips::D8:
- return 16;
- case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
- return 17;
- case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
- case Mips::D9:
- return 18;
- case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
- return 19;
- case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
- case Mips::D10:
- return 20;
- case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
- return 21;
- case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
- case Mips::D11:
- return 22;
- case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
- return 23;
- case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
- case Mips::D12:
- return 24;
- case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
- return 25;
- case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
- case Mips::D13:
- return 26;
- case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
- return 27;
- case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
- case Mips::D14:
- return 28;
- case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
- case Mips::HWR29:
- return 29;
- case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
- case Mips::D15:
- return 30;
- case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
- return 31;
- default: llvm_unreachable("Unknown register number!");
- }
- return 0; // Not reached
-}
-
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
//===----------------------------------------------------------------------===//
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