[llvm-commits] [llvm] r147336 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Craig Topper]

Author: ctopper
Date: Wed Dec 28 21:20:51 2011
New Revision: 147336

URL: http://llvm.org/viewvc/llvm-project?rev=147336&view=rev
Log:
Remove some elses after returns.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=147336&r1=147335&r2=147336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 28 21:20:51 2011
@@ -5161,9 +5161,10 @@
     // the rest of the elements.  This will be matched as movd/movq/movss/movsd
     // depending on what the source datatype is.
     if (Idx == 0) {
-      if (NumZero == 0) {
+      if (NumZero == 0)
         return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
-      } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
+
+      if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
           (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
         if (VT.getSizeInBits() == 256) {
           EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2);
@@ -5172,12 +5173,14 @@
           return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
                               DAG, dl);
         }
-        assert (VT.getSizeInBits() == 128 && "Expected an SSE value type!");
+        assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
         Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
         // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
-        return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
-                                           DAG);
-      } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
+        return getShuffleVectorZeroOrUndef(Item, 0, true,
+                                           Subtarget->hasXMMInt(), DAG);
+      }
+
+      if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
         Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
         if (VT.getSizeInBits() == 256) {
           EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2);
@@ -5186,7 +5189,7 @@
           return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
                               DAG, dl);
         }
-        assert (VT.getSizeInBits() == 128 && "Expected an SSE value type!");
+        assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
         Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
         Item = getShuffleVectorZeroOrUndef(Item, 0, true,
                                            Subtarget->hasXMMInt(), DAG);