[llvm-commits] [llvm] r147017 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsISelLowering.cpp

[Akira Hatanaka]

Author: ahatanak
Date: Tue Dec 20 17:56:43 2011
New Revision: 147017

URL: http://llvm.org/viewvc/llvm-project?rev=147017&view=rev
Log:
Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147017&r1=147016&r2=147017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 17:56:43 2011
@@ -199,6 +199,10 @@
 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
 
+/// Double Word Swap Bytes/HalfWords
+def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
+def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
+
 def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
 
 let Uses = [SP_64] in
@@ -316,3 +320,5 @@
 // Sign extend in register
 def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>;
 
+// bswap pattern
+def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=147017&r1=147016&r2=147017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Dec 20 17:56:43 2011
@@ -221,8 +221,10 @@
   if (!Subtarget->hasBitCount())
     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
 
-  if (!Subtarget->hasSwap())
+  if (!Subtarget->hasSwap()) {
     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
+  }
 
   setTargetDAGCombine(ISD::ADDE);
   setTargetDAGCombine(ISD::SUBE);