[llvm-commits] [llvm] r147004 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64ext.ll

[Akira Hatanaka]

Author: ahatanak
Date: Tue Dec 20 16:40:40 2011
New Revision: 147004

URL: http://llvm.org/viewvc/llvm-project?rev=147004&view=rev
Log:
32-to-64-bit sext_inreg pattern.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/mips64ext.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=147004&r1=147003&r2=147004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Dec 20 16:40:40 2011
@@ -215,6 +215,8 @@
 
 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
                   "sll\t$rd, $rt, 0", [], IIAlu>;
+def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
+                  "sll\t$rd, $rt, 0", [], IIAlu>;
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
@@ -311,3 +313,6 @@
 def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
 def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
 
+// Sign extend in register
+def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>;
+

Modified: llvm/trunk/test/CodeGen/Mips/mips64ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64ext.ll?rev=147004&r1=147003&r2=147004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64ext.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64ext.ll Tue Dec 20 16:40:40 2011
@@ -9,3 +9,11 @@
   %conv = zext i32 %add to i64
   ret i64 %conv
 }
+
+define i64 @sext64_32(i32 %a) nounwind readnone {
+entry:
+; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
+  %conv = sext i32 %a to i64
+  ret i64 %conv
+}
+