[llvm-commits] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading: Obvious fixes.

[Duncan Sands]

Hi Stepan,

> For 'load' I fixed the next:
>
> Next string will always wrong for non round types. For 2 x i7 it returns 1 byte!
> unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
>
> I just replaced it with this one:
>
> unsigned Stride = SrcVT.getScalarType().getStoreSize();
>
> This code just calculates proper size in bytes.

I think it is pointless trying to fix things for <2 x i7> and friends until it
is decided how they should be represented in memory.

Ciao, Duncan.

>
> -Stepan
>
> 15.12.2011, 04:48, "Dan Gohman"<gohman at apple.com>:
>> On Dec 14, 2011, at 12:57 PM, Stepan Dyatkovskiy wrote:
>>
>>>   Hi all. Please find some obvious fixes for<n x i1>  ..<n x i7>  vectors.
>>>   I fixed 'load' expansion, since there was improper stride calculation.
>>>   I also fixed some assertion for trunc store. Assertion dropped for trunc stores with non simple MemoryVT. MemoryVT<n x i1>  will never became simple in ToT. I inserted the store expansion in this case.
>>
>> At least the load part of this patch is wrong. PR1784 specifically says that
>> vector elements are to be bit-packed.
>>
>> Dan
>>
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