[llvm-commits] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading: Obvious fixes.

[Dan Gohman]

On Dec 14, 2011, at 12:57 PM, Stepan Dyatkovskiy wrote:

> Hi all. Please find some obvious fixes for <n x i1> .. <n x i7> vectors.
> I fixed 'load' expansion, since there was improper stride calculation.
> I also fixed some assertion for trunc store. Assertion dropped for trunc stores with non simple MemoryVT. MemoryVT <n x i1> will never became simple in ToT. I inserted the store expansion in this case.

At least the load part of this patch is wrong. PR1784 specifically says that
vector elements are to be bit-packed.

Dan