[llvm-commits] Patch: new backend for Hexagon processor

[Jakob Stoklund Olesen]

On Dec 9, 2011, at 10:28 AM, Tony Linthicum wrote:

>> +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td
>> 
>> +// FIXME: the register order should be defined in terms of the preferred
>> +// allocation order...
>> +//
>> +def IntRegs : RegisterClass<"Hexagon", [i32], 32, (add (sequence "R%u", 0, 9),
>> +                                                       (sequence "R%u", 12, 28),
>> +                                                        R10, R11, R29, R30,
>> +                                                        R31)>
>> 
>> You don't need to shuffle registers here just to put the callee-saved registers last in the allocation order. The register allocator does that automatically.
>> 
> 
> Those are actually reserved registers.  R10 and 11 are discussed above.  29 is SP, 30 is FP, 31 is LR.

RegisterClassInfo handles that too.

If you run llc -debug-only=regalloc, you will see some 'AllocationOrder(RC) = [...]' messages go by.  That is the final allocation order computed for your register classes.

It filters out reserved registers and moves callee-saved aliases to the end.

/jakob